Abstract: A high voltage output stage amplifier that maximizes the output voltage swing when the peak-to-peak output voltage signal is higher than the supply voltage used in the signal conditioning circuits of the amplifier. The amplifier allows the maximum peak-to-peak swing on the output stage by shifting the quiescent voltage of the output stage to the midpoint of the output supply voltage. The shift is accomplished by tapping an offset current at the input of the error integrating stage of the amplifier proportional to the difference in the two power supply voltages.

Abstract: A more efficient memory access is provided by providing fast access to words on the same physical row (wordline) in memory whether sequential or not, by, after issuance of an address, the detection of whether the current access is on the same physical memory row as the previous access and accordingly allows a different number of wait states, dependent on whether the access is on the same row or not.

Abstract: A system and method for interworking a net communication beginning with a proxy protocol and allowing retention of the fullest feature set for enhanced communications between devices. The system within a communications network, receives and analysis the protocol capabilities received by components attempting to establish a communications link and establishes a new proxy protocol based upon commonality of features.

Abstract: An embodiment of the instant invention is a method of fabricating an electrical device having a structure overlying a semiconductor substrate which is planarized using chemical mechanical planarization, the method comprising the steps of: forming a layer of material over the semiconductor wafer; polishing the layer of material by subjecting it to a polishing pad and a slurry which includes peroxygen; and wherein the slurry additionally includes a stabilizing agent which retards the decomposition of the peroxygen in the slurry. Preferably, the stabilizing agent is comprised of: pyrophosphoric acids, polyphosphonic acids, polyphosphoric acids, Ethylenediamine Tetraacetic acid, a salt of the pyrophosphoric acids, a salt of the polyphosphonic acids, a salt of the polyphosphoric acids, a salt of the Ethylenediamine Tetraacetic acid and any combination thereof. In addition, the stabilizing agent may be comprised of: sodium pyrophosphate decahydrate, sodium pyrophosphate decahydrate, and/or 8-hydroxyquinoline.

Abstract: A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the bond pad; at least one second dielectric layer or stack disposed under the first dielectric layer; and a reinforcing metal structure disposed into the second dielectric layer such that the patterns of the metal structure and the second dielectric layer comprise a uniformly flat interface towards the first dielectric layer. The patterns of the metal structure and the second dielectric layer comprise feature sizes and fine pitches used in the integrated circuit.

Abstract: A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a notch (11) having a wall disposed in the wafer and extending to the perimeter which includes a preferably rounded apex (5) interior of the perimeter and a pair of rounded intersections (7, 9) between the wall and the perimeter. The notch is formed with a tool (23) for forming rounded corners in the semiconductor wafer which includes a body of a material having a hardness greater than the semiconductor wafer which has a generally rounded or paraboloidally shaped front portion having a forwardmost tip (25) portion and a wing portion (27) extending outwardly from the body and having a taper narrowing in the direction of the forwardmost tip portion. The wing portion can be one or more spaced apart wing members or the wing portion can be a single member which extends completely around the tool axis.

Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+&tgr;j), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+&tgr;j), i=N−2N−1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2) and the first and second input signals. The correction circuit produces a first symbol estimate ({tilde over (S)}1) in response to the first and second estimate signals and the first and second input signals.

Abstract: The present invention utilizes a plurality of transistors configured such that the drain/well diode of the PMOS switch is not forward biased during any part of the charge pump cycle. In one embodiment a plurality of transistors are coupled between the drain, source and well of the PMOS switch such that the well of the PMOS switch is connected to a voltage that is one base-emitter voltage drop (Vbe) less than the higher of either the source voltage or the drain voltage. Since the well is always a single Vbe below the higher of the source voltage or the drain voltage, the gate-well diodes of the PMOS switches are prevented from becoming forward biased, thereby reducing current drain and resulting in improved efficiency of the charge pump.

Abstract: A wireless local area network (LAN) adapter (20) that optimizes the length of message packets, for example according to the IEEE 802.11 standard, and in an environment having interfering transmissions (BL1 et seq.), is disclosed. The disclosed adapter (20) executes an adaptive process by way of which an adjustment to the packet length is derived based upon rate measures for the most recent two trial packet lengths. The rate measure corresponds to a packet success rate for that packet length, determined either from an estimating function or by actual measurements, multiplied by a ratio of the data portion of each packet to a total packet length including interpacket spacing. Upon convergence as the adjustment becomes smaller, the optimized packet length for best data rate given the present interference. A method of determining the need for packet length optimization is also disclosed, in which the actual packet error rate is compared against an expected packet error rate based upon signal-to-noise ratios.

Abstract: Standby power consumption of storage cells is improved by ramping the wordline voltage down, allowing the addressed storage cell to reach a more stable voltage before reading.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A charge pump circuit is provided for reducing the voltage ripple and EMI associated with prior art circuits. The charge pump circuit is configured with at least one current source for suitably controlling the charging and/or discharging current in the charge pump capacitors the currents of the current sources are determined by the load current requirements, rather than the on-resistance of any switches or the ESR of any capacitors, thus allowing a significant reduction of the peak current drawn from the power supply as well as the peak current injected into the output reservoir capacitor. The charge pump circuit can be configured with a current source in series with the input supply voltage to control the total current in the charge pump. In addition, the charge pump circuit can be configured with current limited switches for controlling the total current.

Abstract: A method generates a list of allowed states in a cache design by applying each input transaction sequentially to all found legal cache states. If application of an input transaction to a current search cache results in a new cache state, then this new cache state is added to the list of legal cache states and to a list of search cache states. This is repeated for all input transactions and all such found legal cache states. At the same time a sequence of input transactions reaching each new cache state is formed. This new sequence is the sequence of input transactions for the prior cache state and the current input transaction. The method generates a series of test sequences from the list of allowed states and their corresponding sequence of input transactions which are applied to the control logic cache design and to a reference memory. If the response of the control logic cache design fails to match the response of the reference memory, then a design fault is detected.

Abstract: A method of image encoding using subband decomposition followed by plus zerotree coding with a symbol replacement for significant coefficients.

Abstract: A digital to analog converter includes a network of impedance components having a plurality of nodes having associated voltages. A tap is coupled to one or more associated one of the plurality of nodes to source or sink electrical current relative to the associated node(s). A switching system is operative to couple a selected one of the nodes to an output according to a digital input word and thereby provide an analog voltage corresponding to the digital input.

Abstract: An analog-to-digital converter (ADC) (12) having a nonlinear transfer function with a unique mapping. The ADC (12) is adapted to produce a digital output signal for a plurality of analog input signals, and a transfer function modifying circuit (14) is coupled to the ADC circuit (13). The transfer function modifying circuit (14) is adapted to modify the ADC circuit (13) transfer function (34) to have a unique mapping. The ADC (12) transfer function has multiple transfer function segments with varying slopes. Further disclosed is a method for designing an ADC (12) having a nonlinear transfer function, and a method for calibrating an ADC (12).

Abstract: An integrated circuit having a pinout configuration, having a first configuration of pins and a circuit to change the integrated circuit to a second configuration of pins.

Abstract: An enhanced gradient dragout system conserves plating chemicals, including precious metals by providing a series of tanks with cascading rinse solutions having a flow rate controlled by heating the first tank to increase the evaporation rate. A portion of the concentrated solution in the heated tank is returned to the process tank. The system minimizes the requirements for clean rinse water, and the need for emptying contaminated rinse tanks with associated recovery and disposal environmental and cost issues. The low cost system is flexible and the process is adapted to the material and process requirements of the plating line.

Abstract: A receiver (54) comprising an input for receiving an RF signal (FIG. 7) centered at a first frequency and having a bandwidth. The receiver also comprises a first mixer (62) for producing a first output signal. The first output signal results from mixing the RF signal with a signal having an energy spreading portion (p(t)) and a down-converting portion (c(t)). Moreover, this first output signal comprises a self-mixing DC signal (c(t)p(t) self-mixing DC component) and a down-converted and energy spread RF signal (FIG. 11). The receiver further comprises a second mixer (70) for producing a second output signal by mixing a signal responsive to the first output signal with the energy spreading portion of the signal. The second output signal comprises two signals, namely: (1) a baseband signal (down-converted RFA1) responsive to the down-converted and energy spread RF signal; and (2) a portion of the spread DC signal (spread DC).

Abstract: A method and display system for using the light (110) passing through the spokes of a color wheel (100). The light is a mixed and rapidly changing color. Adding all of the spoke times produces white, but adding a subset creates color artifacts. The spoke times cannot all be added at the same time without altering the white point of the display. The spoke times are added in a sequence and the sequence is altered over time for the same pixel such that the pixel converges to white over time. The pattern of spoke bits is arranged so that as adjacent spoke bit pixels are added, the net spoke light converges to white. The patterns are also varied so that as more and more spoke bit periods are turned on, the net spoke light converges to white. Each spoke bit period adds n-LSBs of white light intensity, so as each spoke bit period is added, n−I LSBs of white light are subtracted from the white data.