Abstract: The present invention provides a wireless network including a master processing device (14) for generating information and broadcasting the information through wireless, transmission of signals and a plurality of client processing devices (18) having circuitry for receiving the information from the master processing device (14) and transmitting other information to the master processing device (14). The master processing device (14) selects one of the plurality of client processing devices (18) to acknowledge the receipt of the information from the master processing device.

Abstract: A control used in a two stage HVAC system has a power supply from a 24 VAC transformer which is full wave rectified (D1, D2, D3, D4) to create DC voltages for a microcontroller (U1) and relays (K1-K3). All of the control information needed for the two stage control system is sent to the control from a room thermostat (12) having first and second stage cooling signal terminals (Y1, Y2) over a single line by connecting a diode between the Y1, Y2 terminals creating separate microprocessor recognizable signals.

Abstract: An improved wafer level encapsulated micro-electromechanical device fabricated on a semiconductor wafer and a method of manufacture using state-of-the-art wafer fabrication and packaging technology. The device is contained within a hermetic cavity produced by bonding a silicon wafer with active circuits to an etched silicon wafer having cavities which surround each device, and bonding the two wafer by either thin film glass seal or by solder seal. The etched wafer and thin film sealing allow conductors to be kept to a minimum length and matched for improved electrical control of the circuit. Further, the device has capability for a ground ring in the solder sealed device. The devices may be packaged in plastic packages with wire bond technology or may be solder connected to an area array solder connected package.

Abstract: An on-screen display with variable resolution capability permits respective parts of a screen to be processed according to their respective resolution requirements. For any active window in the on-screen display, the data format used in memory to represent the pixels of that window can be determined, thereby permitting the window resolution to vary from window to window.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A method of measuring the motion in video image data for a pixel uses both field-difference and frame-difference motion values to generate a motion value having increased accuracy. Image data (806) from the same pixel in a prior row of the same field (906) is compared to image data (808) from the same pixel in the prior row of the prior frame (908), and the absolute value of the difference is compared to the absolute value of the difference in image data (802) from the same pixel in a following row of the same field (902) and image data (804) from the same pixel in the following line of the prior frame (904). The minimum of these two values is the minimum frame-difference motion value which is input into a logical mixer. Also input into the logical mixer is the minimum field-difference motion value which may be determined by comparing data (802, 806) from the same pixel of an adjacent line of the same field (902, 906) with image data (810) from the same pixel of the same line of the prior field.

Abstract: The present invention provides an apparatus, system and method of improving the bias response time for pre-amplifier circuits which utilize noise reduction capacitors 275. The system uses a quick recovery circuit 210 electrically connected to the capacitive node 216 of the pre-amplifier circuit. The quick recovery circuit 210 comprises a gain amplifier 218 with a resistive input and a controlled current source 219. The controlled current source corresponds to adjustments in a controlled current source 225 of the pre-amplifier and is electrically connected to the resistive input of the gain amplifier 218. The gain amplifier 218 can be selectively switched 211 to operatively connect an output to the capacitive node 216 of the pre-amplifier circuit.

Abstract: A data processing system having a central processing unit (CPU) with address generation circuitry for accessing a circular buffer region in a non-aligned manner is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory ports. A data transfer address for each load/store instruction is formed by fetching the instruction (600), decoding the instruction (610) to determine instruction type, transfer data size, addressing mode and scaling selection.

Abstract: A method to implant NMOS polycrystalline silicon in embedded FLASH memory applications is described. In the method the polycrystalline silicon region (130) that will used to form the gate electrode of the NMOS transistor is doped simultaneously along with the source line in the FLASH memory array.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed over a semiconductor substrate and having a conductive feature comprised of tungsten, the method comprising the steps of: forming a nucleation layer over the semiconductor substrate by introducing a combination of WF6, H2 and a plasma; and forming a tungsten layer on the nucleation layer by means of chemical vapor deposition. In an alternative embodiment, an insulating layer is formed on the substrate and situated between the nucleation layer and the substrate. Preferably, this embodiment additionally includes the step of forming a nitrogen-containing layer under the nucleation layer by introducing a combination of WF6, N2, H2, and a plasma. The conductive feature is, preferably, a conductive gate structure, and the insulating layer is, preferably, comprised of: an oxide, a nitride, an insulating material with a dielectric constant substantially higher than that of an oxide, and any combination thereof.

Abstract: A method for characterizing a VCM assembly includes measuring a first response of the VCM assembly (100), removing a first conducting part of the VCM assembly (102), and measuring a second response of the VCM assembly with the first conducting part removed (104). Then, the method includes using curve fitting techniques (110) with the determined VCM compensation parameters to construct a model of the VCM assembly.

Abstract: Disclosed are radio frequency (RF) interference cancellation techniques that effectively estimate RF interference to the data signals being received using a frequency domain model, and then remove the estimated RF interference from the received data signals. Improved techniques for digitally filtering multicarrier modulation samples to reduce sidelobe interference due to the RF interference are also disclosed.

Abstract: A processor core is provided that is a programmable digital signal processor (DSP). The microprocessor is operable to execute a sequence of instructions obtained from an instruction bus and has program counter circuitry for providing a first instruction address to the instruction bus. An instruction buffer is operable to hold at least a first instruction of the sequence of instructions obtained from the instruction bus. Breakpoint event generation circuitry is connected to the instruction bus and is operable to detect a designated mark instruction and a designated chain instruction in the sequence of instructions. Tag circuitry is associated with the instruction buffer and is operable to hold a mark tag and a chain tag, and is further operable to be set in response to the breakpoint event circuitry. An instruction execution pipeline is connected to receive the sequence of instructions from the instruction buffer register along with respective mark tags and chain tags from the tag circuitry.

Abstract: A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

Abstract: A method of creating or fabricating a composite preform wherein a mixture of a catalyst and a first epoxy resin is applied to at least one layer of fibers, preferably in the form of a fabric, mat or unidirectional tape. A plurality of stacked layers is formed from layers of fibers with applied mixture thereon, preferably in a mold. The layers are pressurized and/or heated to reduce the viscosity, such as but not limited to melting, of the first epoxy resin and catalyst and then allowed to fuse together to form a preform. The preform in the closed mold is impregnated with a mixture of a second epoxy resin and a polycyanate to cause cross-linking, the cross-linking including the first epoxy resin. The first and second epoxy resins may be the same.

Abstract: Device for estimating the frequency offset in a signal received by a differential demodulator of a mobile-telephone set, intended for implementing the method according to one of claims 1 to 3, characterized in that it has means (1) for calculating an error signal &egr; on the basis of the phase &phgr; of the output signal of the demodulator and the ideal phase &phgr;o of this signal, means (4) for establishing the absolute value (ABS) of the error signal &egr;, means (2, 5, 7) for calculating an estimate of the average of the error signal &egr; calculated over a certain number of samples, from which estimate nFO-RAW bits are taken, means (3, 6, 8) for calculating an estimate of the average of the absolute value of the error signal &egr; over a certain number of samples, from which estimate nQ-RAW bits are taken, and means (10) for modelling a frequency-offset function &OHgr;(FO-RAW, Q-RAW) on the basis of the said estimates.

Abstract: A support pillar 426 for use with a micromechanical device, particularly a digital micromirror device, comprising a pillar material 422 supported by a substrate 400 and covered with a metal layer 406. The support pillar 426 is fabricated by depositing a layer of pillar material on a substrate 400, patterning the pillar layer to define a support pillar 426, and depositing a metal layer 406 over the support pillar 426 enclosing the support pillar. A planar surface even with the top of the pillar may be created by applying a spacer layer 432 over the pillars 426. After applying the spacer layer 432, holes 434 are patterned into the spacer layer to remove any spacer material that is covering the pillars. The spacer layer is then reflowed to fill the holes and lower the surface of the spacer layer such that the surface is coplanar with the tops of the support pillars 426.

Abstract: A suspended printed inductor (SPI) connected in parallel to a suspended interdigital capacitor (SIC) so as to form a parallel resonant circuit that is nearly independent of variations in PCB etching tolerances. This combination of SPI and SIC functions to resonate at a center frequency and with similar parallel resonant circuits can be used to form RF filters having any desired order. Using the parallel resonant combination of SPI and SIC, a RF filter can be constructed whose electrical properties are nearly insensitive to variations in PCB parameters and etch processing. The sensitivity of the spiral suspended printed inductor in combination with the suspended printed interdigital capacitor to PCB parameters such as dielectric constant and PCB height is greatly reduced. Further, the parallel combination of suspended printed spiral inductor and suspended interdigital capacitor is nearly insensitive to PCB etching tolerances. SPIs and SICs are characterized by the absence of a ground plane.

Abstract: The method is for programming a memory cell in an array of cells having a plurality of bit lines, each with bit-line coupled cells, and a plurality of word lines, each with word-line coupled cells. A word line-bit line combination identifies a target cell. Each cell has a drain, source, gate and floating gate arrayed upon a base common to the cells, all of which cooperate to establish a floating gate-to-source field in each cell. The method includes the steps of: (a) applying a select signal to a word line and a bit line coupled with the target cell; (b) providing an adjusted signal to the bit-line coupled cells to decrease strength of the floating gate-to-drain field for the bit-coupled cells; (c) programming the target cell; and (d) maintaining the adjusted signal at least until the programming is complete.

Abstract: A buried-channel PMOS device is fabricated simultaneously with a surface-channel device if the gate is doped N-type while the NMOS gates are doped and the P+ source/drain doping is blocked from the “high” P-channel device. In the normal process the “high” PMOS is not fully self-aligned. However, when the PMOS process includes a lightly-doped drain (PLDD), the LDD doping is self-aligned.