Abstract: A method of forming an electrical interconnect through a via to electrically couple two electrically conductive layers and the device. There are provided a pair of electrically conductive layers and an electrically insulating layer between the pair of electrically conductive layers having a via extending between the pair of electrically conductive layers. A layer of titanium is formed covering the walls of the via and extending onto one of the pair of electrically conductive layers. A thin layer of titanium nitride with a poor step ?? technique is formed covering the titanium on the walls but not covering the titanium on the one of the pair of electrically conductive layers. The remainder of the via is filled with aluminum. The layer of titanium and the layer of titanium nitride preferably extend out of the via and between the electrically insulating layer and at least one of the pair of electrically conductive layers.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A system (10) is disclosed for cleaning a vertical furnace (12) pedestal (34) and cap (36) including at least one inlet conduit (40) in fluid communication with a pressurized cleaning medium source (46). The system also includes at least one exhaust conduit (42) in fluid communication with a negative pressure source (48). A boat assembly (30) may be positioned such that the at least one conduit (40) is operable to direct cleaning medium at the boat assembly (30) to dislodge contaminate particles associated with the boat assembly. The exhaust outlet (42) then evacuates the cleaning medium and any dislodged contaminate particles. The system may operate automatically within a closed processing environment and after each process cycle.

Abstract: A radio frequency filter system includes a first acoustic resonator (54, 56) for a first frequency and a second acoustic resonator (54, 56) for a second frequency. An acoustic reflector array (102, 152, 202) is coupled to an electrode of the first acoustic resonator (54, 56) and to an electrode of the second acoustic resonator (54, 56). The acoustic reflector array (102, 152, 202) includes a plurality of reflector layers (112, 152, 210). A first reflector layer (112, 152, 210) is operable to reflect a signal at substantially the first frequency. A second reflector layer (112, 152, 210) is operable to reflect a signal at substantially the second frequency.

Abstract: A method and device for placement of sound sources in three-dimensional space via two loudspeakers. This technique uses an efficient implementation which consists of binaural signal processing and loudspeaker crosstalk cancellation, followed by panning into the left and right loudspeakers. For many applications, the binaural signal processing and crosstalk cancellation can be performed offline and stored in a file. Because, in this situation, panning is the only required operation, this technique results in a low-computation, real-time system for positional 3D audio over loudspeakers.

Abstract: A voltage converter circuit includes a first transistor (M1) having a drain connected to receive an unregulated input voltage (Vin), a gate connected to receive a feedback control signal (4), and a source connected to a first conductor (5). An inductor (6) having a first terminal coupled to the first conductor (5) and a second terminal use connected to produce a regulated output voltage (Vout) on an output conductor (7). A feedback control circuit (190) coupled between the gate of the first transistor (M1) and the output conductor for regulating switching of the first transistor in response to the regulated output voltage (Vout).

Abstract: A digital to analog converter (40) includes a pulse width modulator (14) and a class-D amplifier (16). The class-D amplifier (16) includes a low pass filter (34). A differential signal is available from two nodes (outp, outm) on the amplifier. Common mode compensation circuitry (42) generates a compensation signal during periods where a PWM signal is not being generated to maintain a common mode average value of (Avdd +Avss)/2 from the nodes, without affecting the differential signal.

Abstract: An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG.

Abstract: A data summing scan cell includes an exclusive OR gate, a multiplexer and a flip-flop connected in series. Serial input data is input to one of three inputs of the multiplexer and serial output data is output from the flip-flop. Functional data from the related combinational logic is input to a second input of the multiplexer and an input of the exclusive OR gate. The output of the flip-flop is input to the other input of the exclusive OR gate. The flip-flop can contain response data from an upstream circuit that is not used as stimulus data for the related combinational logic. The data summing scan cell prevents the loss of that response data in a capture of response data from the related combinational logic.

Abstract: A method for simultaneously producing areas of paraelectric states and areas of ferroelectric states on a single thin film layer, thereby reducing the number of processing steps required to produce integrated chips containing both standard capacitors and non-volatile memory devices from the number of steps needed using the conventional approach. A device containing both ferroelectric capacitors and non-ferroelectric capacitors using a single thin film as the dielectric.

Abstract: A CMOS output driver with a DC feedback circuit architecture that changes the output impedance of the driving transistors as the output voltage transition progresses. The output voltage slew rate is then controlled by limiting the gate voltages (node of Ng and Pg) of the output driver transistors during the transition.

Abstract: A method for fabricating inductors and transformers on integrated circuits. A magnetic material is formed on the semiconductor substrate. The magnetic material comprises a suspension of magnetic material in an insulator. A metal film is formed that forms at least one coil around the magnetic material forming an inductor structure. Two adjacent coils can be linked with the magnetic material to form a transformer.

Abstract: The present invention includes a circuit to maintain a constant voltage on a storage element such as a capacitor at the output of a regulator during an emergency power condition. It includes a detector to detect the emergency condition and to generate a fault signal in response to the emergency condition, a one-shot time delay circuit to delay the enabling of a regulator in response to the fault signal, and a second delay unit to delay the enabling of the load of a regulator to accommodate the non-zero recovery time of a regulator. These two time delay units are able to bypass the noisy switching on the fault signal so that the maintained voltage on the storage capacitor will not droop and can be reliably used for such purposes as head retract and spindle brake under a noisy power emergency situation.

Abstract: A method and system for performing a timing recovery acquisition of a sinusoidal preamble with reduced loop latency by effectively bypassing the FIR filter out of the timing loop. The method is implemented by estimating the FIR filter's (201) phase shift through knowing its coefficients a priori while also determining the phase error at the FIR filter's input. Because of the non-symmetric settings of the coefficients the phase shift through the FIR may not be zero. It reduces the latency of a non-data tracking timing loop by eliminating latency due to the FIR filter (201) itself. The coefficients can be either programmed in memory (205) or adapted as part of an LMS application. The estimate avoids the use of multiply operations, using add operations and a single divider. The estimated partial phase errors are then summed in a “FIR bypass-mode” phase detector (204) yielding total phase shift.

Abstract: A digital-to-analog conversion circuit (105) includes a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output. Hereby, the digital-to-analog conversion circuit (105) according to the invention emulates a delta-sigma digital-to-analog converter having both high speed and high resolution.

Abstract: A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified, such that NOPs instructions are aligned in the same slot from one instruction to the next for a series of instructions. This modification permits memory access to be disabled so that those instructions are not fetched.

Abstract: This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a first predetermined set of address bits. A second decoder selectively powers one of the X rows corresponding to a second predetermined set of address bits. Multiplexers select the powered memory bank for data access. Thus one of the plural memory banks is powered and selected for memory access corresponding to the first and second predetermined sets of bits of the received address. This memory system is preferably a cache memory including a further column of memory banks for cache addresses and cache control data including at least a cache valid tag. A multiplexer selects one row corresponding to the second predetermined set of address bits.

Abstract: A Viterbi type decoder which discards paths with metrics more than a distance from the smallest metric with the distance determined by the smallest distance between paths in the trellis.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder bail attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: A socket (1) has a base (10) which forms a recess (10d) for receiving a support member (12). The support member (12) has a recessed surface (12a) for carrying a contact film (14) and has bores for mounting spring contact elements (15). The spring contact elements engage contact members (14b) of contact film (14) from below the film. An adapter (13) has a seat (13b) for a BGA package (2) for exposing solder balls (2a) to contact members (14b) from a location above the film. Socket terminal pins (11b) are electrically connected to spring contact elements (15) through circuit paths (13c) on a pitch expansion substrate (11). A cover (20) and a compression member (30) apply a force to the package.