Abstract: CMOS semiconductor dynamic logic (300) is disclosed, comprising dynamic logic circuitry (302) and tunneling structure circuitry (328) coupled to the dynamic logic circuitry; where the tunneling structure circuitry is adapted to hold a node (308) voltage stable by compensating leakage current originating from said dynamic logic circuitry.

Abstract: A pipelined analog-to-digital converter includes a first stage 700 of an analog-to-digital converter having a first resolution. The first stage 700 includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages 200. The first and subsequent stages 700 and 200 are pipelined together to provide a digital output signal.

Abstract: Device for recovering synchronization on a signal transmitted to a mobile-telephone receiver, including phase-estimator means (47, 49) for the absolute value (ABS) and the sign (SIGN) of the transmitted signal, estimation processor (64) for processing the output signals of the estimators (47, 49), a sequencer (67), one input of which is connected to the output of the processor (64) and one output of which applies a mode signal to the processor, another output of the sequencer (67) being connected via a sampling-time generator (68) to the sampling-time control inputs of the estimators (47, 49).

Abstract: Magnetoresistive, MR, heads and giant magnetoresistive, GMR, heads are used in hard disk drive storage systems. The heads have a pinned layer whose magnetic orientation, if incorrect, gives rise to data read errors. A pinned layer reset method and circuit is provided to restore the magnetic orientation of the pinned layer by applying a reset pulse to the MR head. The circuit employs the existing low frequency cutoff capacitor in the initial amplification stage of the preamplifier to charge the magnitude of the reset pulse. The magnitude of the pulse is programmable by selecting bits in the existing write current digital to analog converter. The head select input transistor applies the pulse to the MR head. The pulse width is programmable as is the discharge rate. The settling value of the pulse is determined by the existing read current digital to analog converter value.

Abstract: A semiconductor device comprising a thermally conductive foil including a chip mount portion having first and second surfaces; an integrated circuit chip attached to said first surface; a body of encapsulation material molded around said chip and said first surface such that it leaves said second surface exposed; and said second surface comprising means for forming thermal contact, thereby creating a path for dissipating thermal energy from said chip. Said means for thermal contact comprise a configuration of said second surface suitable for direct thermal attachment to a heat sink. Alternatively, said means for thermal contact comprise a configuration of said second surface suitable for thermal attachment including solder balls between the chip and the heat sink.

Abstract: An improved write drive circuit which provides an adjustable writer drive current and overshoot transient for a H-bridge drive circuit in a hard disk drive. The invention uses a variable capacitor circuit to give an initial boost to the write driver transistors. In a preferred embodiment, the capacitance of the variable capacitor is controlled by a word written to the disk drive pre-amp over the serial control port.

Abstract: A technique for detecting three modes of video input signal and outputting a vertical sync signal based on the input signal. In a first mode, a standard video signal is received and a line counter is used to decode and output the vertical sync. In a second mode where a non-standard signal is received, line counter cannot be used, but a vertical sync is detected and output. In a third mode, no video input signal is received, yet a vertical sync is output in free-running mode so that a blank screen is displayed.

Abstract: A method and system for applying a surface treatment to an object. The system comprises: a source chamber (106) for holding a source of surface treatment material (102); a deposition chamber (112) enclosing the object to be treated (104); a recovery chamber (108); a supply of carrier gas (110); conduit (116) connecting the source chamber (106) to the deposition chamber (112) and the deposition chamber (112) to the recovery chamber (108) and for controlling the flow of the carrier gas between the source chamber (106), the deposition chamber (112) and the recovery chamber; and a heater (124) for heating the source chamber (106), the source of surface treatment material (102), the deposition chamber (112), an upper portion (120) of the recovery chamber (108), the carrier gas, and the conduit (116). When heated, the source material (102) evaporates into the carrier gas and is carried to the deposition chamber (112) where is attaches to the surface of the object being treated (104).

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A video wire bonder system includes a processor (12) coupled to an imaging station (14), an input device (16), a display (18), and a memory (20). Processor (12) generates an image overlay (30) having a graphical representation of each video wire bond between a bonding pad (34) of a semiconductor die (21) and a lead finger (35) of an associated lead frame (22). Processor (12) generates a template (28) comprising an organization of video wire bond parameters associated with each video wire bond, and stores template (28) in memory (20). Display (18) displays image overlay (30) to provide visual feedback to an operator while the operator is programming template (28).

Abstract: The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at least a portion of the collector region. The method further comprises forming a diffusion blocking layer over the base region, and forming an emitter polysilicon region over the diffusion blocking layer. The diffusion blocking layer reduces an amount of diffusion from the emitter polysilicon region into the base region, thereby allowing improved process control and emitter/base doping profile, leading to improved transistor performance. In addition, the present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region.

Abstract: An integrated circuit (10, 60, 110, 210) is fabricated according to a method which includes the steps of providing a structure (12, 112, 212) having a top surface (13, 113, 213), and forming spaced first and second sections (16-18, 67-69, 72-73, 126-127, 231-232) on the top surface. The first and second sections have side surfaces (21-26, 81-88, 131-134, 241-244) thereon. A respective sidewall (31-36, 91-98, 141-144, 251-254) with a sublithographic thickness is formed on each side surface. Then, a further section (42A-42D, 101A-101D, 152, 268) is formed in the region between the sidewalls on the first and second sections, for example by introducing a selected material between those sidewalls, and by then removing any portion of the selected material which is higher than the upper ends of the sidewalls.

Abstract: A method and system for adjusting the brightness and contrast of a digital pulse-width modulated display without scaling the input image data. Brightness is adjusted by changing the duty cycle of a displayed pixel either by altering the bit display durations, or by turning the pixel on during blanking periods 36. The contrast ratio may be altered by changing the display duration of at least one of the MSBs differently than the display duration of at least one of the LSBs. Contrast may be increased by extending the MSB display periods 50 and shortening the LSB display periods 52. Contrast may be decreased by shortening the MSB display periods 56 and extending the LSB display periods 58. The color tint of the displayed image may be altered by individually changing the brightness of the constituent colors.

Abstract: A method and apparatus for recovering from an unstable oscillating condition in a delta-sigma A/D converter modulator circuit. A modulator circuit is disclosed having integrator stages, each having a first switch across the input terminals of the integrator stage and a second switch across the output terminals of the integrator stage. In another embodiment of the invention, the integrator stage comprises a differentially structured operational amplifier having a first restore switch coupled across the input terminals, a second restore switch across the output terminals, and four disconnect switches, one each coupled between the operational amplifier inputs and ends of the first restore switch and between the operational amplifier outputs and ends of the second restore switch. In operation, an unstable condition detector monitors an output of the A/D modulator circuit and generates a restore signal to the integrator stages upon detection of an unstable condition.

Abstract: An operational amplifier input stage includes a first differential input transistor and a second differential input transistor receiving a differential input voltage. A first translinear loop is coupled to the first differential input transistor and a second translinear loop is coupled to the second differential input transistor. The first and second translinear loops are operable to supply an instantaneous current to the respective first and second differential input transistors to sufficiently charge capacitances therein during slewing conditions.

Abstract: A method for forming a MOS transistor using a disposable sidewall spacer process. A gate dielectric (20) and a gate structure (25) is formed on a semiconductor substrate (10). Insulator films (30) and (35) and formed and a LOCOS type film (80) is formed on the substrate (10). A spacer structure (86) is formed on the gate structure (25) and implants are performed to form the source drain (50), drain extension (110), and pocket regions (120).

Abstract: A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42.

Abstract: Changes in the concentration of a chemical, such as a gas, are determined using a non-linear chemical sensor which is subject to shifts in calibration over time. In order to minimize errors caused by such shifts in calibration a first infrared signal (Ig(1)) is measured and using an absorption value under an assumed chemical concentration (C(1)), a zero chemical signal Io(1) is calculated using the known physical law and mathematical relation Absorption=1−Ig/Io. A second infrared signal (Ig(2)) is then measured and the absorption value is calculated using the previously calculated zero chemical signal. A second concentration (C(2)) is then determined and the change in concentration is calculated by subtracting C(2) from C(1).

Abstract: A method of fabricating an integrated circuit (10, 51, 61, 71, 81, 91) includes forming on the upper surface (13) of a substrate (12) a part (18) which has thereon a side surface (19). A plurality of sidewalls (22, 27 and 83-84) are then formed in succession, outwardly from the side surface. A plurality of successive implants (21, 26, 31, 73-74, 87-88, 93-94) are introduced into the substrate, where a respective different subset of the sidewalls is present when each implant is created. The formation of sidewalls and implants may be carried out in an alternating manner, followed by removal of the sidewalls. Alternatively, removal of the sidewalls and formation of the implants may be carried out in an alternating manner. The width of each sidewall may be sublithographic, and the cumulative width of all sidewalls may be sublithographic.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).