Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: A pyroelectric detector system, the pyroelectric detector element therefor and the method of making the detector element which comprises an integrated circuit (1) and a pyroelectric detector element (7) coupled to the integrated circuit and thermally isolated from the integrated circuit. The element includes a lead-containing pyroelectric layer having a pair of opposing surfaces and having a thickness to provide a resonant cavity for radiations in a predetermined frequency range. A bottom electrode (5) opaque to radiations in the predetermined frequency range is secured to one of the pair of opposing surfaces and a top electrode (9, 11) is secured to the other of the pair of opposing surfaces which is semi-transparent to radiations in the predetermined frequency range. The top electrode is taken from the group consisting of platinum and nichrome. The lead-containing pyroelectric layer is preferably lead titanate.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A method is provided for extracting parasitic data in a hierarchical manner from a trial layout of the integrated circuit. Intracellular parasitic data representative each cell type used in the integrated circuit is extracted only once, regardless of the number of times the cell is instantiated in the integrated circuit. For each instance of each cell, a portion of intercell signal lines that are routed over that instance of the cell are cut out in cookie cutter fashion by specifying an area in the trial layout corresponding to the instance of the cell such that the portion of intercell signal lines within the area can be processed apart from the remaining portion of the intercell signal lines.

Abstract: A water soluble thermoplastic wiring board spacer for temporarily supporting an electrical component in fixed spaced relation to a printed wiring board which comprises a toroidally shaped spacer composed of a water soluble injection molded thermoplastic material. The material is preferably a polymer and the preferred polymer is a blend of partially hydrolyzed polyvinyl alcohol resin and fully hydrolyzed polyvinyl alcohol resin. The spacer has a melting temperature determined by the ratio of partially hydrolyzed polyvinyl alcohol resin to fully hydrolyzed polyvinyl alcohol resin and a solubility rate in water determined by the ratio of partially hydrolyzed polyvinyl alcohol resin to fully hydrolyzed polyvinyl alcohol resin. The spacer can have a plurality of spaced apart ridges and recessed surfaces on a surface thereof.

Abstract: A protocol and associated circuitry operable for efficiently extending serial bus capability in system environments is disclosed. The protocol is designed to coexist and be fully compatible with existing serial bus approaches, and in particular an example of application of the invention to a backplane system utilizing the 1149.1 IEEE standard serial bus is detailed. The circuitry and protocol required to couple any one of the boards on the backplane to the serial bus master without modifying the existing serial bus protocol, without adding additional signals, and without affecting the throughput rate of the serial bus is described. The invention advantageously allows the serial bus master to select, communicate with, and deselect backplane boards so that high level test functions may be simultaneously executed and monitored. Additional preferred embodiments are also disclosed.

Abstract: An FeRAM in which sensing occurs without a dummy cell, using an unselected bitline as a reference. The read cycle includes two opposed pulses on the drive line: the first pulse provides a data-dependent signal out of the selected cell, and the second pulse restores the bit line to a level such that the DC bias voltage on an unselected bitline provides an optimal reference.

Abstract: A word line structure for a dynamic random access memory (DRAM) cell comprises a generally planar substrate and a plurality of mesa-shaped active regions formed on the substrate and protruding outwardly a given distance therefrom. Each of the mesa-shaped active regions has two word-line-receiving regions formed within it. A plurality of substantially straight and parallel word lines are also included; two of the plurality of word lines are embedded in the two word-line-receiving regions formed in each of the mesa-shaped active regions. The inner surfaces of the word lines are located inwardly of the outer surfaces of the mesa-shaped active regions. The structure further includes an insulation layer positioned on the substrate and which forms a plurality of isolation regions between the plurality of mesa-shaped active regions.

Abstract: A capacitor dielectric with multiple layers of differing high dielectric constant materials such as SrTiO3 and BaSrTiO3 in which an inner layer has a higher dielectric constant but also higher leakage current than outer layers on each side of the inner layer which have lower leakage currents but also lower dielectric constants.

Abstract: A process for forming a polysilicon line having linewidths below 0.23 &mgr;m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., deep UV lithography). The BARC layer (30) is etched with an etch chemistry of HBr/O2 using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using the same etch chemistry having a selectivity of approximately one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below the practical resolution limit of the lithography tool. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).

Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: Data processing apparatus 10 supporting circular buffers CB includes address storage ARx for holding a virtual buffer index and offset storage BOFxx for holding an offset address. Circular buffer management logic 802 is configured to be operable to apply a modifier to a virtual buffer index held in the address storage to derive a modified virtual buffer index and to apply a buffer offset held in the offset storage to the modified virtual buffer index to derive a physical address for addressing a circular buffer. By employing virtual addressing to a buffer index for a circular buffer management, it is possible to make efficient use of memory resources. One or more circular buffers can be located contiguously with respect to each other and/or other data in memory, avoiding fragmentation of the memory. The buffer index forms a pointer for the circular buffer.

Abstract: An analog switch includes two complementary MOS field-effect transitors (10, 12) whose source-drain circuits are located in parallel between the input terminal (18) and the output terminal (20) of the switch. A control signal for controlling the switch is applied to the gate of the MOS field-effect transistor (12) of the one channel type directly and to the gate of the MOS field-effect transistor (10) of the other channel type via a negator (16). Between the input terminal (18) and output terminal (20) of the switch the series source-drain circuits of three MOS field-effect transistors (22, 24, 26) are inserted, whereby the MOS field-effect transistor (24) located in the middle of the series circuit has a channel type opposite that of the other two MOS field-effect transistors (22, 26). The gates of all MOS field-effect transistors of the other channel type are each interconnected.

Abstract: The invention relates to a DC/DC converter operating on the principle of a charge pump, comprising at least one charge pump capacitor and several controllable switches connected thereto. The switches are actuated by a control circuit with an oscillator. A skip mode comparator signals the charge pump alternatingly ON and OFF depending on the condition of the output voltage of the converter. Prior art converters featured high output current spikes and a heavy output voltage ripple. The converter in accordance with the invention reduces these problems by a regulator circuit which receives the control signal of the comparator and converts it into a signal characterizing the momentary ON/OFF duration ratio of the charge pump with which it controls the ON resistance of at least one of the switches so that the ON/OFF duration ratio of the charge pump can be set to a predetermined design value, at which the output current spikes of the charge pump are reduced.

Abstract: An operational amplifier includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second input to the second unbalanced differential amplifier (32).

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: The purpose of the present invention is to provide a clamping circuit which has a simple circuit design, with which the clamping voltage range can be easily adjusted, and which can operate at reduced power consumption, as well as interface circuit that makes use of the clamping circuit. NMOS transistor NT1 and diode D1 are connected in series between the feed line of power source voltage Vcc and input terminal Tin, and diode D2 and PMOS transistor PT1 are connected in series between input terminal Tin and ground voltage GND. The divider voltages VND1, and VND2 obtained from resistive elements R1, R2 and R3 connected in series are applied to the control terminals of transistors NT1 and PT1, respectively. Also, transistor NT2 is connected in parallel to resistive element R2. By means of control voltage VB input to the control terminal of NT2, the divider voltages are controlled, and the range of the clamping voltage can be controlled.

Abstract: A buffer circuit includes a chain of a plurality of inverters. A first inverter has transistors with a size to present a first predetermined capacitive loading at its input. This is selected with regard to the target operating frequency of the driving circuit (typically a flip-flop) and the transistor size selected for this driving circuit. Each inverter has transistors with a size a predetermined size factor greater than the transistors of a preceding inverter. The first inverter has transistors the size factor larger than the driving circuit. The size factor is preferably 3. The number of inverters in the chain is selected so that the last inverter has transistors with a size to drive its output capacitive loading with a maximum rise and fall time corresponding to the target frequency. If the number of inverters is even, then the buffer input is connected to a normal output of the driving circuit.

Abstract: A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

Abstract: A disk rotates and information is stored on the disk. An arm accesses the information and a fly height controller controls the height of the arm with respect to the disk as the disk rotates.

Abstract: Fixed gain amplifiers have particular use in the read channel of hard disk drives. A CMOS fixed gain amplifier 18c having a constant gain over the large dynamic range of hard disk drive applications is provided by incorporating super follower transistors M3 and M4 into the input stage of the fixed gain amplifier. The super follower transistors are folded into the output stage of the amplifier. The differential current through the degeneration resistor RE1 travels through the super follower transistors M3 and M4 and into the current mirrors I5 and I6. Thus the ac differential current goes directly to the cascoded stage, into the load resistors RL1 and RL2, and to the output load.