Abstract: An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plasma etch and cleanup processes used to pattern interconnects. In a preferred embodiment, the refractory metal 240 reacts with the conducting layer 210 to form an intermetallic 245 which further enhances the endurance of the metallization against stress-induced rupturing and via-induced electromigration. The disclosed structures and methods are particularly advantageous in “zero-overlap” designs, and aggressive pitch patterns where linewidth and corrosion control are critical, but are also advantageous in “Damascene” pattern definition applications.

Abstract: Fixed gain amplifiers have particular use in the read channel of hard disk drives. A CMOS fixed gain amplifier 18c having a constant gain over the large dynamic range of hard disk drive applications is provided by incorporating super follower transistors M3 and M4 into the input stage of the fixed gain amplifier. The super follower transistors are folded into the output stage of the amplifier. The differential current through the degeneration resistor RE1 travels through the super follower transistors M3 and M4 and into the current mirrors I5 and I6. Thus the ac differential current goes directly to the cascoded stage, into the load resistors RL1 and RL2, and to the output load.

Abstract: Device for monitoring the periodicity of the messages sent over a multiplexed data-transmission network, in particular of a motor vehicle, characterized in that it includes a memory (4) for storing object messages which are received from the network and each have a value (8) indicating the reception deadline of the message, local clock means (9) which are synchronized by a periodic internal signal and continuously generate a local time-value signal, means (13) for comparing each message-reception deadline value (21, 22, 23) with the local time value and for generating an overdue signal when the value indicating the reception deadline of the message is less than or equal to the local time value, and means (15) for generating a signal, intended for an external microcontroller (5) and indicating that the message has not been received, on the basis of the overdue signal.

Abstract: A circuit is designed with a correction circuit (350) coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2), and a plurality of input signals from an external source along plural signal paths. The plurality of input signals includes a first and a second input signal (Rj1, Rj2) The correction circuit produces a first symbol estimate in response to the first and second estimate signals and the first and second input signals. The correction circuit produces a second symbol estimate in response to the first and second estimate signals and the first and second input signals. A combining circuit is coupled to receive a plurality of first symbol estimates including the first symbol estimate and a plurality of second symbol estimates including the second symbol estimate.

Abstract: To offer a technique that can form electrodes in a composite device without using a lift-off method. In the manufacture of a composite device 2 in which a wafer 50 that has a sacrificial layer 51 is used, a mask film 66 that has been patterned is formed; patterning is given to a structural layer 54, the sacrificial layer 51 is etched from the area that is exposed, a movable part 11 is formed in an area where said sacrificial layer 51 is removed, and a fixed part 10 is formed in an area where the sacrificial layer 51 remains; also, a thin metallic film 60 is formed and patterning is given before forming the mask film 66, with electrodes 37 for an external electrical connection being formed. A protective film thin titanium tungsten film 64 is formed on the surface of said thin metallic film 60, with the thin metallic film 60 being protected during etching of the sacrificial layer 51.

Abstract: An apparatus and method thereof for sampling multipath signal data in a receiver. The apparatus includes a plurality of demodulators coupled in parallel, each of the plurality of demodulators receiving digital baseband signal data and demodulating the digital baseband signal data, a controller coupled to the plurality of demodulators, and a timer coupled to the controller. The timer generates a controller interrupt at a specified frequency. The controller interrupt causes the controller to sample demodulated signal data from the plurality of demodulators. The specified frequency is greater than the symbol rate.

Abstract: A method for forming a metal interconnect having a self-aligned transition metal-nitride barrier (124). After the metal interconnect lines (118) are formed, a transition metal (120) is deposited over the surface of the metal interconnect lines (118) and reacted in to form a metal-compound (122). The metal-compound (122) is then annealed in a nitrogen ambient to form a barrier layer (114) at the surface of the metal interconnect lines (118).

Abstract: An integral computer hard drive microactuator support comprising a unitary member of solid material. The support includes a frame portion surrounding and defining an opening portion, and a platform portion disposed within the opening portion. Four fixed-fixed beam portions connect the platform portion to the frame portion, the fixed-fixed beam portions being generally rectangular in cross section and substantially straight along their length.

Abstract: A frequency synthesizer that can accurately compensate for ripple current. The frequency synthesizer 1 having a PLL loop containing an oscillator 31 and a charge pump circuit 35 has a detector circuit 40 and a delay circuit 39. The detector circuit 40, by detecting a ripple current with a superimposed compensating current, detects the time difference between the output time of the compensating current and the output time of the ripple current, and since the delay circuit 39 delays one or both of the output time of the compensating current and the output time of the ripple current based on that detection result, the time difference for the output times can be made small, and if a compensating current is supplied that is equal to the ripple current, it becomes possible to accurately remove the ripple current.

Abstract: A rail-to-rail differential amplifier includes first and second input terminals, and an output terminal and an input stage including differentially connected N-channel first and second input transistors, and differentially connected P-channel third and fourth input transistors. A P-channel first cascode transistor has a source coupled to a first supply voltage to the drain of the first input transistor. An N-channel cascode transistor has a source coupled by a second resistive element to a second supply voltage and to the drain of the third input transistor. A first gain boost amplifier has an output coupled to a gate of the first cascode transistor, a first input coupled to the source of the first cascode transistor and the drain of the first input transistor, and a second input coupled to a drain of the second input transistor and a bias control circuit.

Abstract: An ion implanting architecture (60). The architecture comprises an arc chamber (64) having an interior area (64i). The architecture also comprises a plurality of electron sources (66, 68) disposed at least partially within the interior area. Each of the plurality of sources comprises a conductive plate (72, 80) operable to emit electrons into the interior area and a heating element (70, 78)for transferring heat to the conductive plate.

Abstract: A metallization structure, and associated method, for filling contact and via apertures to significantly reduce the occurrence of microvoids and provide desirable grain orientation and texture. A modified barrier structure is set forth for contact apertures, and a modified liner structure is set forth for via apertures. The metallization fill structure for contact apertures includes a first wetting or glue layer of refractory metal on the contact aperture, a layer of TiN on the first wetting layer, a second wetting layer of plasma-treated refractory metal on the barrier layer, a layer of CVD Al on the second wetting refractory metal layer, and a PVD Al alloy to fill the contact aperture. The fill structure for via apertures includes an initial plasma-treated refractory metal liner deposited on the via aperture. A CVD Al liner is positioned on the initial refractory metal liner. A PVD Al alloy layer is positioned on the CVD Al liner to fill the via aperture.

Abstract: A method and circuit (16) for driving a polyphase dc motor (14) of the type used in a mass data storage device (10) includes a commutator (55) for commutating drive voltages among windings (44-46) of the dc motor (14). In each commutation cycle, drive voltages are applied to two windings and a current summed from currents induced by the drive voltages is sunk from a third winding. A circuit (76) is provided for pulse width modulating the drive voltages during successive phase commutation cycles in respective pulse width modulated (PWM) cycles, and a circuit (66) is provided for measuring an amount of energy delivered to the motor from a beginning of each PWM cycle. A circuit (78-80, 70-72) terminates the drive voltages in a PWM cycle when the circuit (66) for measuring measures a predetermined amount of energy that has been delivered to the motor during the PWM cycle.

Abstract: A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.

Abstract: A method of forming an ultra-thin gate oxide (14) for a field effect transistor (10). The gate oxide (14) is formed by combining an oxidizing agent (e.g., N2O, CO2) with an etching agent (e.g., H2) and adjusting the partial pressures to controllably grow a thin (˜12 Angstroms) high quality oxide (14).

Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.

Abstract: A circuit breaker (10) is shown having a movable electrical contact (36) adapted to move into and out of engagement with a stationary electrical contact (38, 40). A current carrying thermostatic trip member (42) has a portion movable in response to changes in temperature with a motion transfer member (46) transferring the motion to latch/catch mechanism (20, 24, 30, 32). The catch portion (30, 32) comprises a generally U-shaped adjustment element (30) formed of thermostatic material whose legs are fixed to the base (32a) of a catch member (32) which in turn is pivotably mounted in the casing of the circuit breaker. The bight (30c) of the adjustment element is free to move in response to temperature changes relative to the catch member. Overcurrent will cause the thermostatic trip member to transfer motion to the bight of the adjustment element causing the adjustment element and catch member to pivot and release a latch to thereby open the circuit breaker.

Abstract: A digital differential receiver IC that rejects the inter-symbol interference (ISI) that is imposed upon differential digital signals when long runs of a digital state (0 or 1) are transmitted over long cables. The ISI-rejecting differential receiver IC is implemented in either bipolar technology (n-p-n or p-n-p) or in insulated gate FET technology (p-channel or n-channel). The primary differential pair of transistors is connected to a secondary differential pair of transistors through a filter network so that a high pass “shelf” filter transfer function exists between the differential input signals and the output signals. This transfer function mitigates ISI by reducing the gain for long runs of a digital state (low frequencies) and enhancing the gain for the state transition edges (high frequencies).

Abstract: A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

Abstract: A circuit (40) and method for applying drive voltages to a voice coil motor (VCM) (22) of a mass data storage device (10) has two driver sets, each having a high side driver (HSD) (42,46) and a low side driver (LSD) (44,48) connected to the VCM (22). Each driver set has two SENSEFETs (50,52), each having a power FET and a sense FET. A circuit (106,104) is provided for sensing a sense current in the sense FET of the LSD, and a circuit (60,76,74) is provided for increasing the bias on the gates of the SENSEFET (52) in the LSD when the sense current falls below a predetermined level (VREF). Also, a circuit (113,114,110) is provided for driving a predetermined current in the SENSEFET of the HSD when the sense current falls below the predetermined level. Thus, a current at the predetermined level always flows in the SENSEFETs (50,52).