Abstract: Improved techniques for time domain equalization are disclosed. The improved techniques include (i) improved time domain equalization techniques referred to as poly-path time domain equalization techniques; (ii) improved training methods for training transmitters and/or receivers of a data transmission system; and (iii) techniques for providing time domain equalization to a transmitter side of a data transmission system. These techniques are particularly suitable for time domain equalization in multicarrier modulation systems where channel shortening provided by time domain equalization is particularly needed.

Abstract: An optical sensor array with zone-programmable gain and offset prior to A/D conversion for reducing quantization noise. The circuit comprises a register file which contains digital words for controlling gain and offset according to multi-pixel zones.

Abstract: An output stage of a complementary bipolar operational amplifier includes: a first bipolar transistor 14; a second bipolar transistor 16 coupled to the first bipolar transistor 14; a third bipolar transistor 10; a fourth bipolar transistor 12; a first resistor 42 coupled between a base of the first bipolar transistor 14 and the third bipolar transistor 10; a second resistor 43 coupled between a base of the second bipolar transistor 16 and the fourth bipolar transistor 12; a first current source 26; a second current source 28; a third resistor 40 coupled between the first current source 26 and the third transistor 10; a fourth resistor 41 coupled between the second current source 28 and the fourth transistor 12; a fifth resistor 19 coupled between a base of the third transistor 10 and a common node; a sixth resistor 18 coupled between a base of the fourth transistor 12 and the common node; a first input stage current source 24 coupled to the base of the third transistor 10; and a second input stage current sou

Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: In one embodiment, the present invention provides a method of forming a dynamic random access memory device which utilizes self-aligned contact pads 40a and 40b for the bit line and storage node contacts. A transfer gate 14 is formed at the fact of a semiconductor region 30. The semiconductor 30 includes a bit line contact region 44 and storage node contact region adjacent opposite edges of the transfer gate 14. Transfer gate 14 is surrounded with an insulating material 34/38. A conductive layer 40 is formed over the transfer gate 14, over the bit line contact region 44 and over the storage node contact region. This conductive layer 40 is then etched so that a first portion 40a of the conductive layer 40 provides an electrical contact to the bit line contact region 44 and a second portion 40b of the conductive layer 40 provides an electrical contact to the storage node contact region.

Abstract: A open circuit detection circuit for a hard disk drive write head, wherein the write head receives write drive signals from a write driver, and wherein the write driver generates a write drive signal in response to write control signals. The circuit includes a pulse width detector, generating a latch control signal in response to the detection of a write control signal having a predetermined duration. The circuit also includes a comparator comparing the write drive signal to a predetermined reference level and generating a comparison output signal indicative of whether the write driver signal is more or less than the predetermined level. A latch is coupled to receive the comparison output signal, the latch being clocked in response to the latch control signals. The latch output provides an indication of an open circuit.

Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Abstract: The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

Abstract: A hold circuit for holding a digital switch, having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving the digital switch. The hold circuit includes an inverter having an input connected to the output of the digital switch and having an output, and a variable resistor having a port connected to the output of the inverter and having a port connected to the input of the digital switch. In a preferred embodiment, a bus-hold integrated circuit servicing Insulated Gate FET digital switches can be operated from either of two distinct ranges of supply voltage (VCC). The magnitudes of the holding currents for the higher range of VCC are nearly the same as those for the lower range of VCC. This characteristic is achieved by changing the resistance in the feedback path of the bus-hold circuit according to the applied VCC.

Abstract: A circuit (300) employing metal-oxide-semiconductor (MOS) devices is disclosed. The circuit (300) includes a circuit portion (302) that provides a circuit function, and a body voltage adjust portion (304) which alters the body potential of the transistors within the circuit portion (302). By adjusting the body potentials of the circuit portion (300) transistors, the speed at which the circuit portion (300) can perform its function is increased. A decoder circuit embodiment (800) and sense amplifier embodiments (1200, 1300, 1500, 1600, 1700, 1800, 1900 and 2000) are also disclosed.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

Abstract: A method of communication and the communication system wherein, there is provided a first telephone for receiving information, time-compressing the information, storing the information and transmitting the information to a central station. There is provided at least one and generally a plurality of spaced apart central stations for receiving the time-compressed information from the first telephone, storing the time-compressed information and retransmitting the time-compressed information to a second telephone. A second telephone is provided for receiving the time-compressed information from the central station, one of storing the time-compressed information and, responsive to call-up, time-decompressing and transmitting the time-decompressed information or time-decompressing the time-compressed information and storing the time-decompressed information and then, responsive to call-up, transmitting the time-decompressed information.

Abstract: A DRAM is disclosed that is capable of performing a rapid write-followed-by-read operation. In a preferred embodiment 400, the DRAM includes a plurality of memory banks (402-a402n), a global write bus (424), and a global read bus (426). The global write and read buses (424 and 426) are coupled to each memory bank (402a-402n) by an associated local read/write circuit (428a-428n). In an initial write operation to a first memory bank (402a-402n), input data on the global write bus (424) are latched in a first local read/write circuit (428a-428n) associated with the first memory bank (402a-402n). In a subsequent read operation to a second memory bank (402a-402n), as data are output from the second memory bank (402a-402n) onto the global read bus (426) via a second local read/write circuit (422a-422n), the first local/read write circuit (422a-422n) is simultaneously writing the latched input data into the first memory bank (402a-402n).

Abstract: A socket having a base (2) which can removably mount a BGA package (9) and a plurality of contact members (6) which are arranged in conformity with the pattern of terminal solder balls (11) of BGA package (9) on base (2) and which have a pair of arms (6a) and (6b) that are capable of opening or closing for pressure contact in the state of sandwiching each terminal of BGA package (9). Partition walls (4a) are provided on slider (4) which is capable of moving in a direction normal to the opening and closing direction of arms (6a) and (6b), the partition walls engage with the pairs of arms of the contact maker (6) respectively, with the arms (6a) and (6b) being opened or closed by the movement of the partition wall.

Abstract: The present invention provide a method of implementing bit reversal using a subtree lookup table. In another aspect of the invention, a subtree lookup table is used to implement digit reversal.

Abstract: A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device (10) having at least one metal layer (28) completed. Then, a planarizing dielectric layer (30) is added to the semiconductor device (10). The semiconductor device (10) is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device (10).

Abstract: A delta sigma modulator system includes a delta sigma modulator (9) including a summing circuit (3) having a first input connected to receive an input signal (2), loop filter circuitry (5) having an input coupled to an output of the summing circuit (3), and comparator circuitry (22) having an input coupled to an output of the loop filter circuitry (5) and also having an output coupled to an output (23) of the delta sigma modulator (9). The density of the dither is adjusted in accordance with changes in the magnitude of the input signal. This is accomplished by performing a coarse digital filtering of an output signal (23) produced by the delta-sigma modulator (9), wherein noise present in the output signal (23) produced by the delta sigma modulator (9) causes a probability distribution of the occurrence of pulses constituting a filtered output signal (25) produced by the coarse filtering. A dither disable signal is produced if the filtered output signal (25) is not within a first threshold window.

Abstract: A computer system (12) comprising a first DSL modem (M12) for communicating data packets (MG1, MG2, MG3) with a second DSL modem (M14) after a connection is established between the first DSL modem and the second DSL modem. The data packets are for communication from the first DSL modem to the second DSL modem at a downstream communications rate and for communication from the second DSL modem to the first DSL modem at an upstream communications rate. The computer system further comprises a memory (MEM12) operable to store a computer program (60), where in one embodiment this computer program is an operating system. The computer program is operable to require a data parameter indicating a number of data packets which may be communicated in an instance from the computer program to the first DSL modem for communication to the second DSL modem. Lastly, the computer system further comprises a field (e.g.

Abstract: A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.