Abstract: A circuit (50,100,1 12,1 30) for detecting a fault in a magneto-resistive head (18) includes a transconductance amplifier (52) having an input across which the head (18) is connected. A circuit (130) for determining a ratio of a current in the head, I VMR, to a variable control current, I1, is applied to maintain a substantially constant voltage at an output of the transconductance amplifier (52). The current, IVMR, in the head is a function of the variable control current, I1, The circuit for determining a ratio of a current, IVMR, flowing in the head (18) to the variable control current, I1, comprises first (112) and (100) second current mirrors, the first current mirror (112) mirroring the current flowing in the head (18), and the second current mirror (101) mirroring the variable control current, I1, Circuitry (132,135) is provided that triggers fault indicating output signals if the ratio falls outside a predetermined range.

Abstract: A pipelined analog to digital converter for converting an analog signal to a sequence of digital words, each such word representing a value of the analog signal at a time in a succession of times. The converter includes a sequence of analog to digital converter stages, each such stage generating at least one bit for each such word. A first such stage in the sequence receives the analog signal, and each such stage subsequent to the first stage receives a residue signal from a previous stage in the sequence. Each such stage includes an analog to digital unit that senses a sample of the analog signal and provides one or more bits representing a value of the sample. In at least one of the stages the analog to digital unit comprises a &Sgr;-&Dgr; converter.

Abstract: An integrated circuit and method of fabrication are disclosed for achieving electrical isolation between a spiral inductor and an underlying silicon substrate using standard semiconductor manufacturing process flow. A spiral conductor with square windings is formed in metal layer (20) patterned so that straight runs of successive turns (22, 23, 24) overlie corresponding runs of concentric square rings (16, 17, 18) formed in underlying metal layer (14). A unity gain voltage buffer (30) connects each ring (16, 17, 18) with a respective overlying turn (22, 23, 24).

Abstract: A power converter is comprised of a hysteretic controller including a feedback circuit that monitors the output frequency of the controller, compares it to a reference generated either internally or externally by the user, and then adjusts the hysteresis of the controller accordingly. The adjusted hysteresis levels will then cause the switching frequency to either increase or decrease thereby controlling the switching frequency of the power supply controller and maintaining it at a desired level.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: The invention relates to an integrated CMOS circuit for use at high frequencies with active CMOS components (12) and passive components (16, 18, 20). The active CMOS components (12) are formed in a semiconductor substrate (10) which has a specific resistivity in the order of magnitude of k&OHgr;cm. In the semiconductor substrate (10), and under the active CMOS components (12), a buried layer (22) is formed which has a specific resistivity in the order of magnitude of &OHgr;cm. The passive components (16, 18, 20) are formed in or on a layer (14) of insulating material which is arranged on the semiconductor substrate (10). A conducting contact layer (24) is arranged on that surface of the semiconductor substrate (10) which is not facing the layer (14) of insulating material.

Abstract: A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate array (9) is formed on a semiconductor substrate. Isolations regions (70) are removed and the exposed silicon implanted forming diffused regions (180). The SAS so formed can be configured to function as a resistor element (240).

Abstract: A low-pass filter circuit includes: a first compound transistor device (22) and (24) coupled between an input node (30) and an output node (32); a first transistor (20) coupled to the input node (30), a gate of the first transistor (20) is coupled to a drain of the first transistor (20); a second compound transistor device (36) and (38) coupled between a gate of the first compound transistor device (22) and (24) and the gate of the first transistor (20); a second transistor (34) coupled to the first transistor (20) and having a gate coupled to a gate of the second compound transistor device (36) and (38), the gate of the second transistor (34) is coupled to a drain of the second transistor (34); a current source (26) coupled to the drain of the second transistor (34); a first capacitor (C1) coupled to the output node (32); and a second capacitor (C2) coupled to the gate of the first compound transistor device (22) and (24).

Abstract: A structure having shallow-implanted elevated source/drain regions is formed with doped sidewall spacers. Diffusion of dopants from the sidewall spacers forms a doped region extending from underneath the gate electrode, along the edge of the epitaxial layer, to the doped (and uppermost) regions of the elevated source/drain. Low junction capacitance, is achieved because the shallow implant of the elevated source/drain regions places the junction inside the source/drain region itself. Low source/drain resistance is achieved because the diffused doped region provides a doped path between the shallow implanted region of the elevated source/drain and the channel region. Low source/drain junction depth is achieved because a second spacer can prevent dopant from being implanted through any faceted areas of the epitaxial layer. The doped extensions of the source/drain regions also have exceptionally low junction depth.

Abstract: A method for reading data from an IEEE 1394 serial bus system and storing the data in a FIFO includes partitioning the FIFO into a plurality of registers, each having 32 register bits for the data and a single register bit for a control data bit. To manipulate the system such that reads on a data quadlet involve only one system read on a 32-bit system, a packet token is stored in the initial register in a data packet. This packet token includes the quadlet count in the data packet. The host system need only read the first register in the data packet, the packet token, to determine the number of data quadlets within the data packet. Thereafter, the control data bit need not be read such that only a single read operation is performed for each operation of the read pointer. The last register associated with the packet is the acknowledge register which contains information that is sent back to the transmit node in the system.

Abstract: A domino logic circuit includes a precharge device precharging a precharge node during a precharge phase and a logic block receiving plural input signals to conditionally discharge the precharge node. In this improvement a second precharge device precharges an intermediate node when a particular input signal controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device controlled by a second input signal different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node.

Abstract: A reprogrammable FIFO status flags system for determining the status of a FIFO memory having a storage capacity (depth) D generates a pair of FIFO status flags, PAF (Programmable Almost Full) and PAE (Programmable Almost Empty) that can be reprogrammed multiple times, even after FIFO writes and reads have occurred. Two offset values (‘N’ and ‘M’) are programmed into the FIFO. PAE is high only when the number of words stored in the FIFO equals N or fewer. PAF is high only when the number of words stored in the FIFO equals D minus M or more.

Abstract: A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit (121) has N taps (142-146) arranged to produce a respective plurality of first tap signals from the input signal (111). A first logic circuit (130, 132, 134, 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal (150) in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps (150, 172-184) arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four.

Abstract: An improved memory cell (600) for use in a high-intensity light environment. The memory (600) comprises a substrate (616) capable of generating photocarriers when exposed to radiant energy, at least one transistor (602), at least one capacitor (604), and address node (610) electrically connecting the transistor (602) and the capacitor (604), and an active collector region (626). The active collector region (626) is fabricated in the substrate (616) in a position to allow the active collector region (626) to recombine photocarriers traveling through the substrate (616) thus preventing the photocarriers from reaching the address node (610).

Abstract: A containment device for retaining semiconductor wafers (54) which includes a first housing member (10) having a frame (12), an inner wall (14) and an outer wall (16), the inner wall (14) and outer wall (16) having a spaced apart relationship forming a gap (18) therebetween. The inner wall (14) closely receives the semiconductor wafers (54). The containment device also includes a second housing member (36) that is securably attachable to the first housing member (10) and which has a frame (38) that forms the top of the containment device when the first and second housing members (10, 36) are securably attached together. The first and second housing members are secured by a plurality of latches (20), each with a hook (22) secured to the first housing member which passes through a hole (40) in the second housing member and is releasably secured within the hole by the hook.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the semiconductor substrate, the conductive structure comprised of an oxygen-sensitive conductor and having an exposed surface; oxidizing a portion of the conductive structure (step 313 of FIG. 1); and subjecting the conductive structure to a plasma which incorporates hydrogen or deuterium (step 315 of FIG. 1).

Abstract: A method and system for compressing and decompressing degamma data stored in a read only memory (116). A control processor (114) reads the compressed degamma data from the ROM (116) and decompresses the degamma data. The decompressed data is stored in a set of random access memory degamma lookup tables (118).

Abstract: A method and system for processing video signal. The method and system provide for automatically detecting letterboxing in an input video signal, and scaling a desired portion of the video signal to match a given display device, as well as detecting subtitles in the input video signal and selectively including the subtitles in the desired portion of the video signal. A signal processor (202) receives video image data, calculates image data statistics for each line of the video image, locates at least one desired portion of the video image, scales the desired portion of the video image for display on a display device (116) having a pre-determined aspect ratio.

Abstract: A method for testing a cell in a device for reliability is disclosed. The cell us coupled to a reference voltage and a current source. The method and system comprises measuring a mirrored current through the device at first predetermined gate voltage and measuring a mirrored current through the device at a second predetermined voltage. The method and system includes determining the threshold voltage of the cell and heating the device for a predetermined period of time. Finally, the method and system includes calculating a new threshold voltage if the measured mirrored current is different from the previously measured current. Accordingly, a system and method in accordance with the present invention addresses this drift problem by testing the characteristics of the memory array on a bit by bit basis. A system and method in accordance with the present invention includes a mirrored current source arrangement.