Abstract: A nitride wet etch in which liquid TEOS is flowed directly into the hot phosphoric acid bath before wafer etching begins. This preloads the bath chemistry with silicate ions, and thus helps assure very high selectivity to silicon oxides.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A high-pass filter has a variable resistance which can be varied by a trimming signal and a programming signal. The variable resistance has a common resistance which is controlled by the trimming signal or the programming signal through a common control line.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A control circuit is provided which includes a single programmable terminal for controlling a plurality of modes, functions or parameters in a programmable circuit with a minimum of program elements connected to the single programmable terminal. The program elements may illustratively be resistors, capacitors, inductors or other circuit components. In a first mode, for example, two program elements control a signal generating function in the programmable circuit. In a second mode, a voltage provided internally forces a condition at the programmable terminal to control another signal generating function. In both first and second modes, the values of the program elements, selectable by the user, also determine the particular frequencies of the respective generated signals. In a third mode, the signals generated in the first and second modes are compared to provide a control function.

Abstract: The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.

Abstract: A speed up speech recognition search method is provided wherein the number of HMM states is determined and a microslot is allocated for Hidden Markov Models (HMMs) below a given threshold level of states. A macroslot treats a whole HMM as a basic unit. The lowest level of macroslot is a phone. If the number of states exceeds the threshold level a microslot is allocated for this HMM.

Abstract: A phase separation during solvent evaporation of a solution containing polymer precursors leaves low pressure solvent without polymer precursor in minimal gaps. After polymerization, drive off the low pressure solvent to yield air gaps in the minimal gaps under the polymer.

Abstract: An integrated circuit having a memory cell array in which the strapping of cell components is accomplished within a memory cell. In one embodiment the strapping 750, 752, 756 is placed between the moats 706,724 of transistors that compose cross-coupled inverters within a static random access memory cell.

Abstract: A routing technique for improving device reliability by selectively depopulating solder balls (12) (and their respective solder ball pads (34), vias (32) and traces or lines (30)) from a conventional foot print of a ball grid array (BGA) package, and a BGA package so modified. The routing technique uses the gap resulting from the depopulated solder balls as additional space for routing traces or lines from solder ball pads to an exterior surface of a substrate (14) upon which a semiconductor die (20) is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls on ever shrinking packages, thereby increasing device reliability.

Abstract: A method to create runlength-limited codes from shorter codes having suppression of error propagation by insertion of uncoded bits adjacent error suppression end bits of the shorter code.

Abstract: A controller (800) for a pulse width modulated display system. The controller (800) periodically determining the output of a light source by sampling the output of a light detector (808) an creating a smoothed approximation of the periodic waveform of the light source. A processor (806) in the controller (800) reads a base bit split sequence from a read only memory (804) and modifies the sequence by lengthening or shortening the bit periods described therein in order to compensate for the periodic variations of the light source. The modified bit split sequence is stored in two-port random access memory (802) where it is later accessed by both the processor (806) and a sequencer (304). The sequencer (304) reads the modified bit split sequence from the two-port random access memory (802) to determine when to load each bit of image data into a modulator an-ay.

Abstract: A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).

Abstract: A cross-coupled bandgap circuit (10, 30) generates a stable voltage reference (Vref) at an output port (12, 32). The circuit comprises a cross-coupled current source (14, 34) coupled to a Wilson current mirror (16,36) mirroring a first current through the current source (14,34) to a current sink (18, 38), and also to a voltage generator generating the stable voltage reference. The circuit may be implemented in bi-polar, Bi-CMOS or CMOS circuitry, and is very stable across varying temperatures, varying and noisy operating voltages, between low and high operating voltages, and is stable at low operating currents.

Abstract: The method of the present invention includes the following steps. First, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A photoresist layer is formed over the first dielectric layer. Next, the photoresist layer is patterned to define a gate region. An etching process is performed to the photoresist layer to narrow the gate region. Portions of the first dielectric layer are etched using the residual photoresist layer as a mask. The undoped polysilicon layer is etched using the residual photoresist layer and the residual first dielectric layer as a mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all areas of the substrate.

Abstract: An improved micromechanical device comprising a substrate (104), a deflectable member (102) suspended over the substrate (104), at least one spring-ring (124) supported above the substrate (104); and at least one address electrode (110) spaced apart from substrate (104). The spring-ring (124) resists deflection of the deflectable member (102) when the deflectable member (102) deflects to contact the spring-ring (124). By moving the address electrode (110) off the substrate level, the micromirror is much more immune to particle-caused short circuits, and a planer surface on which to fabricate the mirror (102) is provided without the need to utilize an inverse spacer layer.

Abstract: An orientation apparatus (10) includes a pair of conveyor chains (21a,21b) with pins (22) on alternate links for moving a component tube (40) to a lift station (26,27) where the component tube (40) is rotated until it is in a desired orientation. The component tube (40) is rotated by rollers (30,33) until an index tab (28a) falls into an opening (40a)in the component tube (40), stopping its rotation. The component tube (40) is then lowered onto the conveyor chains (21a,21b) and moved to the end of the apparatus where is it removed from the orientation apparatus. A component tube chamber (50) located above the conveyor chains drops one component tube (40) at a time, utilizing two singulators (58,59), onto the conveyor chains (21a,21b).

Abstract: The described embodiments of the present invention provide a computer docking system and method for connecting a portable computer to a docking station and method for coupling the docking station to an external monitor and an external keyboard and a technique for customizing the hardware configuration in the docking station for optimum performance. In a preferred embodiment, the technique for customizing the program hardware in the docking station is capable of customizing common hardware in various docking stations.

Abstract: A computer controlled system includes a data storage device connected to a host computer using a bus which allows device-initiated bus-mastering. The system has system RAM which is associated with the host computer and which is not part of the data storage device. The data storage device requires certain device operating data/code in the form of device control means and device operating data to be used to control the operation of the device. An arrangement and method for operating the data storage device includes storing at least a portion of the device operating data/code in the system RAM. The arrangement and method further include allowing the host computer and/or the data storage device access to the device operating data/code stored in the system RAM such that the host computer and/or the data storage device may use the device operating data/code to control the operation of the data storage device.

Abstract: A constant voltage generating circuit, with a negative temperature coefficient, is able to generate a stable voltage despite variations in the power supply voltage. The constant voltage generating circuit comprises a reference current source circuit 10B, a diode DX, an amplifier circuit AMP that amplifies the voltage across diode DX and outputs voltage VCS, and current control circuit 20 that controls the current flowing into node N1. Current control circuit 20 comprises transistors QB1 and QB2, which form a current-mirror constant-current source, and a diode QB3 which has the same characteristics as said diode DX. The current control circuit sinks current from node N1 to transistor QB1 and maintains the temperature coefficient of voltage VCS at a negative value. Reference current source circuit 10B is not affected by the change in the power supply voltage VCC and is able to supply a constant current to node N1.