Abstract: A controller for read/write head actuator of a hard disk drive system includes a feedback unit providing a voltage to a servo-actuator motor. The feedback unit includes a first fuzzy logic rule-based algorithm unit for the seek mode and a second fuzzy rule-based algorithm unit for the track mode. In the seek mode, the first algorithm unit, based on present position and delta (velocity) parameters, determines an optimum velocity. A signal representing the optimum velocity is compared with a signal representing the present velocity and an appropriate signals applied to the head actuator unit. The use of the fuzzy logic rule-based algorithm permits a near-minimum seek time even in the presence of non-linear and varying parameters. The output signal from the seek mode apparatus or the output signal from the track mode apparatus is selected based on position and velocity parameters.

Abstract: An oscilator circuit for a integrated circuit memory device to optimize the refresh operating circuit and suppress wasteful power consumption in which the oscillator frequency is set high during high temperatures and the oscillator frequency is set low during low temperatures. A current I1 is generated by means of the current source 100a having characteristics in which it is increased during high temperatures and decreased during low temperatures, and is supplied to the ring oscillator 200.

Abstract: A data storage circuit (50) has a data input (12′) for receiving a data voltage (D″) and a node (44) for receiving an interim voltage in response to the data voltage. The data storage circuit also includes an output enable circuit (34) for providing at least one conditional path coupled to the node and for coupling the interim voltage to the node. The output enable circuit has a transistor (40p) having a first threshold voltage and operable to provide a conductive path along the at least one conditional path. The data retention circuit (46 and 48) has at least one transistor having a second threshold voltage higher in magnitude than the first threshold voltage. The data storage circuit includes a second node (58) for receiving a second interim voltage in response to the first interim voltage. A second output enable circuit (52) provides at least one conditional path for coupling the second interim voltage to the second node.

Abstract: An amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain equal to or very near unity has one plate of a compensation capacitor conventionally coupled to an internal high impedance gain node, but has the other plate of the compensation capacitor unconventionally driven with a buffered version of the input signal. The voltage appearing across the compensation capacitor in response to changes in the input signal is significantly less than that achieved using conventional compensation architectures where the other plate of the compensation capacitor is coupled to an AC ground. Since very little current is required to charge the compensation capacitor, the tail current generated by the input stage can be used instead to charge parasitic capacitances within the amplifier to increase the slew rate.

Abstract: A high power supply ripple rejection internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses an intermediate amplifier stage configured from a common source, current mirror loaded PMOS device to replace the more conventional source follower impedance buffer associated with conventional Miller compensation techniques. Compensation is achieved through use of a small internal capacitor that provides a very low frequency dominant pole at the output of the input stage while effectively pushing out the two other poles at the outputs of the second and third gain stages to a frequency well outside of the unity gain frequency to ensure closed loop stability. High, wide bandwidth PSRR is achieved through an integrated circuit implementation of three voltage gain stages compensated by a nested active Miller compensation technique that does not impedance shunt the output series PMOS pass device.

Abstract: A display memory (15) for a display system (10, 20) having a spatial light modulator (SLM) (16). The memory (15) receives data in pixel format and delivers the data to the SLM (16) in bit-plane format. The memory (15) avoids the need for double buffering by reading out bit-planes that are comprised partly of data from one data from and partly of data from an adjacent data frame.

Abstract: An SLM-based video receiver (10) receives a video input of some standardized format at a signal interface unit (11) and passes the input to a processor (12). The processor (12) performs analog-to-digital conversion if the pixel data is analog and also performs other enhancements to prepare the pixel data for loading into a video memory (14). The pixel data from the processor (12), representing a field of pixel data, is stored into the memory (14) for loading into rows of pixel elements of a spatial light modulator (16). The spatial light modulator (16) receives the pixel data in rows and each individual pixel element responds accordingly. The pixel elements of the spatial light modulator (16) emit light or reflect light from a source (18) and generate a video frame for display on a screen (20). By exploiting the addressing functions of the spatial light modulator (16), the SLM-based video receiver (10) displays a video frame using a field of pixel data.

Abstract: A voltage reference overshoot protection circuit senses unwanted ringing voltage levels in a driven device such as a backplane and controls the gate voltage to a voltage level control transistor such that a ringing output signal produced by an associated output driver is reduced in response to a control signal dependent on the ringing voltage level.

Abstract: A field emission device (10) for reducing the power dissipation of an array (14) includes video controller (12) coupled to array (14) by memory (13), column drivers (16), row drivers (20), and anode power supply (22). Column drivers (16) includes PWM circuit (17) coupled to signal conditioner (18). Signal conditioner (18) receives input digital signal (24) from PWM circuit (17) and generates output digital signal (26) that reduces the frequency of state transitions of signal (24) while maintaining the same duty cycle as that of signal (24). This reduces the power dissipation of parasitic capacitances (36) associated with array (14) pursuant to the equation P=½CV2f.

Abstract: A method for the calibration of a measuring device for the measurement of RF parameters of integrated circuits on semiconductor wafers on which there are a large number of such integrated circuits, which is to be carried out as follows: A calibration semiconductor wafer is produced, containing integrated comparison circuit units which correspond to a plurality of characteristic circuit types, and which may be contacted via measuring points on the surface of the calibration semiconductor wafer. The S two-port parameters of each circuit unit on the calibration semiconductor wafer corresponding to any one circuit type are measured with precision. The measured S two-port parameters are stored. The calibration semiconductor wafer is inserted into the measuring device. The measuring device is then calibrated in such a way as to achieve an optimum impedance match at the measuring probe tips which will be brought into contact with the measuring points of the calibration semiconductor wafer.

Abstract: To reduce the power consumption and to shorten the transmission delay time in a signal line drive for the purpose of transmitting a binary signal. The NMOS transistors 10, 12 are respectively connected as driving switching elements between the transmission end of a complementary pair of bus lines (AL, AL_) and a terminal at the power supply voltage (VSS) of a reference L level. The switching control circuit 14 for the purpose of controlling the ON□OFF switching of the NMOS transistor 10 is constructed of the PMOS transistor 16, the NMOS transistor 18, the inverters 20, 22, the NAND gate 24, and the NOR gate 26. The switching control circuit 34 for the purpose of controlling the ON□OFF switching of the NMOS transistor 12 is constructed of the PMOS transistor 36, the NMOS transistor 38, the inverter 40, the NAND gate 42, and the NOR gate 44.

Abstract: A primary-side power modulator for an isolated switching-mode power supply operating under secondary-side control comprising a pulse width determining circuit for real-time primary-side adjustment of a PWM control signal received from a secondary-side PWM controller. While accepting pulse width commands from an isolated secondary-side PWM controller, the pulse width determining circuit has the ability to reduce the width of the switching pulse in response to primary-side information. The power modulator may further comprise a start-up circuit for ensuring that the primary-side supply voltage is above a minimum under-voltage lock out threshold, a soft start circuit for controlling the power switch at power-up, a pulse receiver for receiving the PWM control signal generated by the secondary-side PWM controller, and a drive circuit for driving an external solid-state power switch with the adjusted PWM control signal.

Abstract: A method for fabricating a gate device includes forming a discrete post on a substrate. The discrete post protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the discrete post. A gate structure is formed and operable to control the access channel to selective couple the first terminal to the second terminal.

Abstract: The system of the present invention having a first module (20) for storing information describing a plurality of data objects (150, 160, and 170), attributes of each of the plurality of data objects, and relationships therebetween; a second module (15) for accepting and processing user queries generating first results data, the first results data including the information describing the plurality of data objects stored in the first module; and a third module (85) responsive to the second module (15) for generating second results data using the first results data, the second results data including the information contained in the plurality of data objects.

Abstract: An improved auto-zeroing circuit for reducing offset currents from high impedance CMOS current drivers. The Auto zero circuit of the present invention contains means to disconnect the output of the current driver from its low impedance load, means to substantially simultaneously connect a capacitor to the output of the current driver, and means to use the output voltage of the current sources during the zeroing mode to adjust the voltage on the capacitor. The capacitor voltage is then used to adjust either of the two output current sources to reduce the offset currents.

Abstract: A method of dispensing a lubricant into a micromechanical device package and a micromechanical device package containing the lubricant. The method comprises the steps of mixing (102) the lubricant, typically a perfluoroalkanoic acid such as perfluorodecanoic acid with a suitable solvent, typically an ether solvent such as tetrahydrofuran or tert-butyl methyl ether. The mixture is allowed to equilibriate (104) before being filtered (106) to remove solid particles. The filtered solution is applied (108) to a surface that will be on the interior of the package, typically the ceramic substrate. The deposited mixture is then cured (110) to remove most, if not all, of the solvent, and the package is sealed (112).

Abstract: A folded-cascode amplifier (30) having a small signal gm being boosted and transferred from the input stage to the output stage to reduce current consumption and expand bandwidth. The amplifier has a pair of second amplifiers (A) operating as boosting amplifiers that provide a pole at its output node, which is at a fairly low frequency. A compensation scheme is employed to introduce a zero to cancel out this pole, and as a side benefit, another zero is brought in which is used to cancel out a second pole of the original folded-cascode amplifier so that bandwidth is actually expanded. Two compensation capacitors (C1, C2) serve two purposes, one, providing a dominant pole to the main amplifier due to a Miller Effect, where the value of the two capacitors are much smaller than for conventional folded-cascode amplifiers, and two, introduce two zeros which cancel out two high frequency poles so that bandwidth is expanded.

Abstract: Disclosed is a process for preparing a semiconductor device comprising the steps of adhering a back surface of a wafer, a front surface of which has been formed a circuit, onto the radiation curable adhesive layer, dicing the wafer into chips, rinsing, drying, irradiating the adhesive layer with radiation to cure said adhesive layer, expanding the adhesive sheet if necessary to make the chips apart from each other, then picking up the chips, mounting the picked chips on a lead frame, bonding, and molding to give such a structure that the back surfaces of the chips are partially or wholly in contact with a package molding resin, wherein the radiation curable adhesive layer comprises 100 parts by weight of an acrylic adhesive composed of a copolymer of an acrylic ester and an OH group-containing polymerizable monomer and 50-200 parts by weight of a radiation polymerizable compound having two or more unsaturated bonds, and the radiation curable adhesive layer has an elastic modulus of not less than 1×109 d

Abstract: To provide a method that can be used to form a high-qualility ferroelectric film by forming good nuclei when using the sputtering method to manufacture a PZT capacitor or other forroelectric capacitors using Ir or other electrode substances in addition to Pt for the electrode. In the method for manufacturing a PZT ferroelectric capacitor CAP, after titanium film 31 is deposited on Ir electrode 6, lead oxide 32 is deposited at a substrate temperature higher than the crystallization temperature of lead titanate using the sputtering method. Lead zirconate titanate 34 is then deposited at a substrate temperature higher than the aforementioned substrate temperature using the sputtering temperature. Afterwards, a heat treatment of the deposited film is performed to produce PZT film 17.

Abstract: A method of detecting object scratching during robotic arm movement of the object. The method includes providing a robotic arm for grasping and placing of an object into a cassette and providing a cassette having an entrance for receiving an object therein. A vibration sensor is placed on at least one of the robotic arm or under the cassette control of the robotic arm is provided in response to a malfunction indication at least one of the vibration sensors. There can further be provided an air flow across the entrance of the cassette with placement of a particle counter at the downstream end of the air flow across cassette entrance, wherein the control of said robotic arm is provided in response to a malfunction indication at least one of the vibration sensors and the particle counter. The control can also be provided in response to both of the vibration sensors or one or both of the vibration sensors and the particle counter.