Abstract: Air-bridges are formed at controlled lateral separations using the extremely high HF etch rate of a gap-fill spin-on-glass such as uncured hydrogen silsequioxane (HSQ) in combination with other dielectrics having a much slower etch rate in HF. The advantages of an air-bridge system with controlled lateral separations include providing an interconnect isolation dielectric which meets all requirements for sub-0.5 micron technologies and providing a device with reduced reliability problems.

Abstract: A circuit is designed with a first transistor (661) having a current path coupled between a supply terminal (32) and a first output terminal (665). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit (679, 685) has first (668) and second (23) input terminals and a second output terminal (681). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit (80) receives the control signal and produces an output voltage at the supply terminal.

Abstract: This is a method for forming a recessed LOCOS isolation region, which includes the steps of forming a first silicon nitride layer between the pad oxide layer and a polysilicon buffer layer and a second nitride layer over the polysilicon buffer layer. In addition, the method for forming LOCOS isolation regions can include the additional steps of forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation regions have provided a low-profile recessed field oxide with reduced oxide encroachment into the active moat region.

Abstract: A floating-gate memory which uses a skewed reference for sensing. The skewed reference preferably has a substantially different VT implant dose than the array cells, and can also have different sizing.

Abstract: An resonator circuit and an integrated circuit including the resonator circuit and method of making. A silicon substrate of a first conductivity type (1) is provided and an integrated circuit TFR circuit (23) is formed on a region of the substrate which includes a stack containing a plurality of alternately non-porous (3,7,11) silicon and porous (5,9,13) silicon layers. A method is provided to deposit layers with alternately opposite conductivity type and convert only one conductivity type but not the other into porous silicon materials. Each of these layers generally has the thickness which is one quarter of an acoutic wavelength of the resonator frequency. A noise isolator (17,19) is disposed along the sidewalls of the stack and extends into the substrate. A region of silicon (29) is disposed on the substrate and separated from the reflector by the noise isolator. At least one of an active and/or passive device (27) is disposed on or in said region of silicon.

Abstract: A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer.

Abstract: In a transceiver unit in which the information is encoded in a plurality of levels, a update unit for an adaptive or equalizer filter unit includes apparatus (51-56) for forming product of error signals and data signals without using a multiplier unit. The plurality of levels is represented by a logic signal format (b2, b1, b0) for five signal levels. The components of the logic signal format (b2, b1, b0) provide the control signals which process the error signals in such a manner as to provide the appropriate product. The only arithmetic unit is an adder unit (56) needed to combine the previous coefficient Wn,t−1 with the product generated by the apparatus (51-56).

Abstract: A process of operating a computer system (100). The computer system (100) has a storage (HDD, 110) holding an operating system (OS) and an application program (APP.exe), a first processor (106) having an instruction set, and a second processor (1730) having a different instruction set. The process includes steps of 1) running (2424) at least some of the operating system (OS) on the first processor (106) so that the first processor (106) sets up for at least part of the application program at run time at least one second processor object (VSP OBJECT 1); and 2) concurrently running the second processor (3310) to access the second processor object (VSP OBJECT1) and thereby determine operations for the second processor (1730) to access second processor instructions for said part of the application program (APP.exe) and data to be processed according to said second processor instructions, and running (2436) the second processor (1730) to process the data according to said second processor instructions.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: An optical matrix switch station (1) is shown mounting a plurality of optical switch units (15, 17), each of which includes a mirror (29), moveable in two axes, for purpose of switching optical beams from one optical fiber to another. A mirror assembly (41) includes a single body of silicon comprising a frame portion (43), gimbals (45), mirror portion (47), and related hinges (55). Magnets (53, 54) and air coils (89) are utilized to position the central mirror surface (29) to a selected orientation. The moveable mirror and associated magnets along with control LED's (71) are hermetically packaged in a header (81) and mounted with the air coils on mounting bracket (85) to form a micromirror assembly package (99) mounted in each optical switch unit.

Abstract: A method of formulating a strong oxidizing solution comprising formulating a strong oxidizing solution having from about 2 to about 5 percent PDSA with concentrated sulfuric acid in the ratio of from about 1:8 to about 1:20 parts by volume and storing the strong oxidizing solution in a container having a space over the solution containing one of a vacuum or a non-oxidizing atmosphere inert to the oxidizing solution. The amount of PDSA is preferably about 4 percent by volume and the ratio is preferably about 1:10 parts by volume. The space over the strong oxidizing solution is preferably a vacuum or substantially all nitrogen.

Abstract: Serial port circuitry (2) for use in a mass data storage device (5) and a method for configuring and operating it are disclosed. The serial port circuitry includes a serial port (2) for providing information from circuitry within the mass data storage device (5) for use external to said mass data storage device and user programmable circuitry connected to the serial port to receive externally applied signals (6) to modify at least one parameter of said mass data storage device (5). The user programmable circuitry preferably includes a sequencer (12, 18, 22) programmed to selectively provide at least two different serial port control outputs (162,212) to modify at least two parameters of said mass data storage device. The sequencer (12, 18, 22) executes pre-established program instructions contained in a RAM (12) to control the mass data storage device.

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. A high energy and low dose blanket phosphorous is implanted in a semiconductor substrate for forming a punch-through stopping layer of the PMOSFET device. A low energy and low dose blanket BF2 implant then adjust both the threshold voltages of the PMOSFET and NMOSFET.

Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

Abstract: A wireless data platform (10) comprises a plurality of processors (12,16). Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler (80) executed on one processor compiles code into native processing code for another processor. A dynamic cross linker (82) links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (90) (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.

Abstract: A fail-safe Input/Output buffer bias circuit for digital CMOS chips provides protection for Input/Output buffers which have high voltages applied to the Input/output node and are subjected to power supply failure resulting in a collapsing supply voltage decaying to zero volts while said Input/output circuit has a high voltage remaining applied to its Input/output node. The Input/output buffer bias circuit is comprised of a sensing circuit and a bias generator circuit which acts to drive protection transistors in a manner which optimally minimizes the voltage impressed on input or output devices under all conditions which could persist in the event of VDD supply voltage failure. Protection circuitry holds all three combinations of voltage stress, gate-to-source, gate-to-drain, and drain-to-source voltages, to acceptable levels.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first silicon layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) silicon-oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium silicon-oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium silicon-oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide. However, the zirconium silicon-oxynitride gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: A system and method is provided for storing a data value by implementation of electrical fuses. Typically, the electrical fuses are provided in a fuse array broken up into a plurality of fuse chains addressable by a control logic circuit. The control logic circuit provides control signals for serially loading data values into the chain. Preferably, the control logic circuit also provides control signals for testing and programming of the loaded data values in addition to subsequently reading the loaded data values. A chain can include a plurality of sub-chains. Each chain or sub-chain includes optional write protection fuse cells, optional read protection fuse cells and at least one data fuse cell. Preferably, one of the optional write protection fuse cells is located first in the chain or sub-chain and one of the optional read protection fuse cells is located last in the chain or sub-chain.