Abstract: The present invention discusses fractional compensation timing circuitry (15) to track a VCO output frequency, fO, and provide highly effective error cancellation in a fractional-N PLL synthesizer. This output frequency tracking is used to suppress spurious sidebands, commonly known as spurs, in both fixed-band and multi-band wireless transceiver applications which use fractional-N PLL synthesizers. Some of the critical parameters which benefit from this type of PLL include switching time, phase noise, and reference feed-through.

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: A high frequency bipolar switching transistor circuit. A first bipolar transistor is provided, having an emitter adapted to receive a voltage, having a base adapted to receive a drive current, and having a collector. A second bipolar transistor is provided, having a base connected to the collector of the first bipolar transistor, having a collector connected to the base of the first bipolar transistor, and having an emitter. An inductor having a first port connected to the common connection node of the collector of the first bipolar transistor and the base of the second transistor, and having a second port connected to the emitter of the second transistor. The common connection node of the emitter of the second transistor and the second port of the inductor form the output of the circuit.

Abstract: A controllable current limiting circuit (30) that, when used with a low precision current limiting circuit (10), will limit the current of the output driver transistor M1 to a relatively flat response over a broad temperature range. The current is limited by setting the voltage across a resistance, R1, to a certain value. To overcome temperature induced variations in this voltage, the compensation circuit (20) generates a current that varies with temperature. This current is injected into a terminal of the resistance, R1. This current is generated in such as a manner to ensure that the current flowing in the output driver transistor M1 is relatively constant over a wide temperature range.

Abstract: A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).

Abstract: A method for selective allocation of power to elements of a circuit comprises identifying at least one element of the circuit for reduced power dissipation and selecting the at least one element. The method further comprises altering an input to the at least one element thereby reducing the power dissipated by the at least one element.

Abstract: A trench isolation structure can be formed in a stack trench capacitor fabrication process by forming a trench region (18) through a buffer layer (16) and an interface layer (12) and into a semiconductor substrate (14). A trench wall layer (20) is grown on inner walls of the trench region (18) and in contact with the interface layer (12). A trench filler layer (28) is formed on the buffer layer (16) and on the trench wall layer (20) within the trench region (18). The trench filler layer (28) is removed from the buffer layer (16) but remains within the trench region (18). A storage dielectric (30) is deposited on the buffer layer (16) and on the trench filler layer (28) within the trench region (18). A field plate layer (32) is deposited on the storage dielectric (30) and within the trench region (18). The field plate layer (32), the storage dielectric (30), the buffer layer (16), and the interface layer (12) lying outside the trench region (18) are removed.

Abstract: In integrated semiconductor manufacturing, semiconductor dies may be packaged in ceramic packages. Such packages typically have a base into which the semiconductor die is placed and typically have a lid which seals the package. A halagen lamp radiant chamber significantly reduces the time it takes to seal the package.

Abstract: A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic.

Abstract: A continuous time filter being operable to boost of an input signal including a first integrator to input the input signal and to integrate the input signal and to output a first integrated signal, a second integrator coupled to the first integrator to input the first integrated signal and to integrate the first integrated signal and to output a second integrated signal, and a third integrator coupled to the second integrator to input the second integrated signal and to integrate the second integrated signal and to output a third integrated signal.

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Abstract: A gasket is provided as a substitute for metal dambars during a process of encapsulating an integrated circuit chip package. The gasket can be in the form of a straight strip for sealing one side of the lead frame or a structure which corresponds in shape and dimension to the entire perimeter of the lead frame. The gasket has grooves formed therein which are defined by projections between adjacent grooves. The depth of each groove is slightly greater than a thickness of the leads. When the gasket is compressed prior to injection of an encapsulation material, the gasket material deforms such that the projections sealingly fill the spaces between leads and the cross-sectional shape of each groove is substantially the same as the cross-sectional shape of the respective lead disposed within the groove.

Abstract: A gasket is provided as a substitute for metal dambars during a process of encapsulating an integrated circuit chip package. The gasket can be in the form of a straight strip for sealing one side of the lead frame or a structure which corresponds in shape and dimension to the entire perimeter of the lead frame. The gasket has grooves formed therein which are defined by projections between adjacent grooves. The depth of each groove is slightly greater than a thickness of the leads. When the gasket is compressed prior to injection of an encapsulation material, the gasket material deforms such that the projections sealingly fill the spaces between leads and the cross-sectional shape of each groove is substantially the same as the cross-sectional shape of the respective lead disposed within the groove.

Abstract: A point-to-multipoint communication system wherein the base station broadcasts the same frequency band signals over multiple sectors of given node. The base station includes a plurality of channel receivers (ch. 1-ch. n) for each sector and a plurality of antennas 36a and 36b selectively coupled to said channel receivers. The subsector antennas have these radiation centers offset from each other to present different coverage over the node.

Abstract: A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

Abstract: A ferroelectric capacitor electrode contact structure comprising an insulator (304) placed over a substrate (302), the insulator (304) containing a source plug (310) and a drain contact (312). An upper plug layer (322) is place over and electrically connected to a drain contact (312). A multi-component oxide layer (324) is placed over an upper plug layer (322). A bottom electrode (326) is placed over a multi-component oxide layer 324. Multi-component oxide layer (324) prevents the silicidation of the bottom electrode (326) of a ferroelectric capacitor electrode contact structure while surprisingly maintaining an ohmic contact from the substrate (302) through the drain contact (312) through the upper plug layer (322) through the multi-component oxide layer (324) to the bottom electrode 326.

Abstract: A method for loading solder particles (14) onto an substrate comprising applying a flux (18) directly onto solder particles (14) either prior to or following adhering the solder particles (14) onto adhesive areas (30) of an adhesive coated film (20). The adhesive areas (30) of the adhesive coated film (20) are oriented to correspond with contact pads (42) of a substrate (16). The adhesive coated film (20) is aligned with the substrate (16) to transfer the solder particles (14) to the contact pads (42). The solder particles (14) may then be reflowed to securely attach the solder particles (14) to the contact pads(42).

Abstract: A method and circuit (40) for tuning a Gm/C filter. A first circuit portion includes a variable current source (52) having a plurality of transistors M15 through M20 coupled to switches SWA through SWMAX. The output capacitor CINT is calibrated iteratively by compensating a calibration capacitor CINTC with the variable current source to tune the Gm/C filter. The transconductance Gm is dependent on a precision external resistor Rext rather than on internal resistors of the Gm/C filter. An algorithm (74) performs the iterative calibrations for the Gm/C filter. The invention is particularly useful for mixed signal or analog circuits.

Abstract: A method of singing voice synthesis uses commercially-available MIDI-based music composition software as a user interface (13). The user specifies a musical score and lyrics; as well as other music control parameters. The control information is stored in a MIDI file (11). Based on the input to the MIDI file (11) the system selects synthesis model parameters from an inventory (15) of linguistic voice data units. The units are selected and concatenated in a linguistic processor (17). The units are smoothed in the processing and are modified according to the music control parameters in musical processor (19) to modify the pitch, duration, and spectral characteristics of the concatenated voice units as specified by the musical score. The output waveform is synthesized using a sinusoidal model 20.

Abstract: Video compression coding with partitioning of data into motion vector data and texture data with reversible Golomb-Rice type codes for the data. Resynchronization markers separate the data types, and the reversible coding permites decoding in both forward and backward directions to minimize data discarded due to errors.