Abstract: An integrated circuit (IC) can include an interface configured to receive packetized data specifying a programming instruction for a memory external to the integrated circuit over a first communication channel. The first communication channel can be an in-band signaling channel also used by the IC when performing a function independent of programming the memory. The IC can include a buffer having a first port coupled to the interface and a second port. The buffer can be configured to store the programming instruction extracted from the packetized data. The IC also can include a programmer coupled to the second port. The programmer can be configured to program the memory over a second communication channel different from the first communication channel responsive to interpretation of the programming instruction from the buffer.

Abstract: In one embodiment, a method for communicating a sequence of data bits is provided. FEC coding is performed on a received sequence of data bits to produce an FEC coded sequence formatted for a first set of N data lanes. The FEC coded sequence includes FEC data blocks, in which each FEC data block has a plurality of data symbols. Alignment markers are added to the FEC coded sequence and the FEC coded sequence is multiplexed to produce a multiplexed sequence formatted for a second set of M data lanes. The multiplexing is performed only at boundaries between the data symbols or the alignment markers. The multiplexed sequence is transmitted on M data lanes.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.

Abstract: Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node.

Abstract: A direct memory access circuit includes a buffer handler configured to store received data within a buffer in a buffer memory coupled to the direct memory access circuit and to generate a descriptor for the buffer. The direct memory access circuit further includes a descriptor handler coupled to the buffer handler. The descriptor handler is configured to determine a descriptor address for the descriptor and to store the descriptor at the determined address within a descriptor memory coupled to the direct memory access circuit.

Abstract: An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.

Abstract: An exemplary method of implementing a circuit design for a programmable integrated circuit (IC) includes, on at least one programmed processor, performing operations including: generating a description of circuit components of the circuit design including first portion of a circuit module that is independent of assignment of resources of the programmable IC; assigning a plurality of the resources of the programmable IC to a plurality of the circuit components including determining at least one resource assignment for the circuit module; and generating a physical implementation of the circuit components for implementation in the programmable IC, including generating a second portion of the circuit module that is dependent on the at least one resource assignment, and combining the second portion of the circuit module with the first portion of the circuit module.

Abstract: A computer-implemented method of updating an installed computer program can include receiving a user input specifying a query against help documents of a documentation system of the installed computer program and executing the query against the help documents. Responsive to determining a query result, usage information for the documentation system can be stored within computer memory of a computer system. The usage information can include at least one entry, wherein the entry includes at least a portion of the query and the query result, thereby specifying an association between the query and the query result. The usage information can be automatically sent to a remote computer system affiliated with a provider of the installed computer program.

Abstract: A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.

Abstract: A filter can include a first channel and a second channel. The first channel can be configured to process a first term and a second term of an input vector using a first coefficient and a second coefficient of the filter. The first channel can be configured to generate a first term of an output vector. The second channel can be configured to process the first term and the second term of the input vector using the first coefficient and the second coefficient of the filter. The second channel can be configured to generate a second term of the output vector. The first and second channels can be configured to operate in parallel.

Abstract: Data-driven processing of a circuit design includes converting each pattern of one or more input patterns from a first format into a second format. Each pattern identifies one or more inputs and one or more outputs and specifies each function that generates each of the one or more outputs from the one or more inputs. Each pattern of the second format is stored in a database. An input circuit design is searched for circuit design elements that match patterns in the database. Data indicative of each pattern in the database that matches a circuit design element is output.

Abstract: An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Abstract: A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a base die and the number of input and output pads on a stacked die. In a first embodiment, a number of through-die vias (TDVs) may be used to implement inter-die signal paths using standard or flexible design rules to maintain statistical TDV yield despite the lack of continuity verification of the inter-die signals paths. In alternate embodiments, programmable multiplexers may be utilized to share one or more inter-die connections between the base die and the one or more stacked die so as to facilitate testing and normal operation of each inter-die connection. In other embodiments, spare TDVs are utilized only during test operations, so as to accommodate the mismatch.

Abstract: A silicon interposer has a plurality of conductive vias extending from a first side of a silicon substrate to an opposite side of the silicon substrate. A plurality of first side scan chain links are disposed on the first side of the silicon substrate. Each scan chain link electrically connects two conducting vias of the plurality of the conductive vias together. In some cases, a test fixture connects the opposite side of the conductive vias together and continuity or resistance is measured. In other cases, scan chain links are formed on the opposite side of the wafer to form a scan chain, which is electronically tested.

Abstract: An apparatus generally relating to a receiver is disclosed. In this apparatus, the receiver includes a phase interpolator, a detector and a slicer. The slicer is coupled to the phase interpolator to provide a sampling signal for a sampling position of the phase interpolator. The detector is coupled to the slicer to receive the sampling signal. The detector is configured to adjust a code of the phase interpolator to adjust the sampling position iteratively in response to the sampling signal to tune the sampling position of the receiver toward an optimum therefor.

Abstract: A configurable transactional memory synchronizes transactions from clients. The configurable transactional memory includes a memory buffer and a transactional buffer. The memory buffer includes allocation control and storage, and the allocation control is configurable to selectively allocate the storage between a transactional buffer and a data buffer for the data words. The transactional buffer stores state indicating each combination of a data word and a client for which the data word is referenced by a write access in the transaction in progress from the client. The transactional arbiter generates the completion status for the transaction in progress from each client. The completion status is either committed for no collision or aborted for a collision. A collision is an access that references a data word of the transaction from the client following a write access that references the data word of another transaction in progress from another client.

Abstract: A decoder in a device receiving data having an error correction code is described. The decoder comprises a memory storing program code having instructions including control signals for decoding an error correction code; an address generator coupled to the memory, the address generator updating an address coupled to the memory for generating a next control signal; and a data processing circuit coupled to receive an instruction from the memory and further coupled to receive syndrome data, the data processing circuit generating error correction values. A method for decoding data having an error correction code is also disclosed.

Abstract: A circuit for asynchronously transmitting data in an integrated circuit is described. The circuit comprises a transmitter circuit generating data to be transmitted at an output; a first register having an input, an output and a clock input, wherein the input of the first register is coupled to the output of the transmitter and the clock input of the first register is coupled to receive a clock signal; at least one asynchronous buffer having an input and an output, wherein the input is coupled to the output of the first register; a receiver circuit coupled to the output of the at least one buffer; and a second register having an input, and output and a clock input, wherein the input of the at least one asynchronous buffer is coupled to the output of the transmitter and the clock input of the second register is coupled to receive the clock signal. A method of implementing of asynchronously transmitting data in an integrated circuit device is also disclosed.

Abstract: An apparatus relating to on-chip noise measurement is disclosed. In such an apparatus, an asynchronous comparator receives a first input and a second input to provide a digital output. A threshold voltage generator receives a first periodic signal and a second periodic signal to provide the second input as an analog voltage responsive to the first and second periodic signals. A sampling circuit is coupled to receive the digital output signal and a third periodic signal. The sampling circuit is configured to sample the digital output signal using the third periodic signal to provide a sampled signal of the digital output signal. A processor is coupled to receive a delay signal and the sampled signal to determine a noise measurement signal for the first input signal.