Abstract: Testing power domains of a circuit design includes correlating, using a processor, a selected power domain of a circuit design having a plurality of power domains with a partial reconfiguration partition and implementing the circuit design within an integrated circuit. The partial reconfiguration partition is implemented within a reconfigurable region of the integrated circuit. A power off state for the selected power domain of the circuit design is emulated by partially reconfiguring the reconfigurable region of the integrated circuit.

Abstract: Methods and circuits are disclosed for backing up the value of a bi-stable circuit included in a set of programmable logic circuits of a programmable IC. The programmable logic circuits are configured to implement logic circuits having functions based on data values stored in a used portion of a plurality of configuration memory cells. The programmable IC includes a backup control circuit configured to back up and restore the value of the bi-stable circuit. In response to a first signal, a first data value stored by the bi-stable circuit is retrieved and stored in a first one of the plurality of configuration memory cells that is unused in implementing the logic circuits. In response to a second signal, the first data value is retrieved from the first one of the plurality of configuration memory cells and stored in the bi-stable circuit.

Abstract: In one embodiment, a matrix multiplication circuit is provided. The circuit includes a plurality of systolic arrays, a pre-processing circuit, and a post-processing circuit. The pre-processing circuit is configured to receive first and second input matrices, and decompose the first input matrix into a plurality of sub-matrices. The pre-processing circuit inputs each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with the second input matrix. The post-processing circuit is configured to combine output of the systolic arrays into a result matrix.

Abstract: An apparatus relating generally to digital-to-analog conversion is disclosed. In such an apparatus, a digital-to-analog converter (“DAC”) device includes a source DAC and a sink DAC selectively coupled to one another. The source DAC provides a first bias to the sink DAC in a sink mode, and the sink DAC provides a second bias to the source DAC in a source mode.

Abstract: In an apparatus, a receiver includes a clock data recovery module to provide a dense distribution of waveform edges across an adjustment range, and an eye scan circuit to obtain samples at a first sample position and a second sample position to provide an error count for a sample count for the samples. An eye scan module, coupled to the receiver, is configured to: scan for the samples at the first sample position of a first type for each of a plurality of sample positions of a second type to obtain an error count for a sample count for each of the plurality of sample positions; locate a threshold BER from the scan; determine an amount and a direction of a sample offset at the threshold BER from a reference location; and adjust either the first sample position or the second sample position responsive to the amount and the direction.

Abstract: An inductive device includes an inductor having an inductance associated therewith, and a tuning ring disposed around the inductor. The tuning ring has an inductance associated therewith, wherein the tuning ring is coupled to the inductor to establish a mutual inductance between the tuning ring and the inductor. The inductance of the inductor, the inductance of the tuning ring, and the mutual inductance between the tuning ring and the inductor contribute to a total inductance of the inductive device. The tuning ring is configurable, and is selectively configured to achieve a certain value for the mutual inductance, and a certain value for the inductance of the tuning ring, without changing a footprint of the tuning ring.

Abstract: An apparatus relating generally to data pattern bias detection is disclosed. This apparatus includes a bias detector. A slicer is coupled to the bias detector to provide an error signal from the slicer to the bias detector. The bias detector is configured to determine a difference between an error input and an error mean for the error signal to detect a presence of correlated data in input signaling.

Abstract: Approaches for configuring programmable resources of a programmable IC are disclosed. A first set of configuration data is loaded using a configuration port of the programmable IC, which also includes input/output (I/O) ports. Programmable resources are configured according to the first set of configuration data to implement a master data link circuit and at least one slave data link circuit. The master data link circuit includes a hardwired communication circuit, and a set of the programmable resources arranged to form a communication control circuit configured to control the communication circuit to provide a data link for communicating data via one of the I/O ports. A second set of configuration data is loaded using the master data link circuit. Programmable resources of the programmable IC are configured according to the second set of configuration data to implement a logic circuit configured to communicate data via the slave data link circuit.

Abstract: Circuits and methods characterize a receiver. The circuit includes a decision feedback equalizer (DFE) circuit, a clock and data recovery (CDR) circuit, a data checker, and an eye-scan controller. The DFE circuit generates a filtered signal from the communication signal. The filtered signal is a sum of the communication signal and a variable weighting of a symbol recently sampled from the filtered signal. The CDR circuit samples a sequence of sampled symbols from the filtered signal. The CDR circuit samples the filtered signal at a variable phase relative to a clock signal. The data checker generates an indication of an error in the sequence of sampled symbols. The eye-scan controller varies the variable weighting and the variable phase through multiple value combinations. The eye-scan controller checks for the indication of the error for each of the value combinations.

Abstract: An apparatus relates generally to multiband power modulation. In such an apparatus, there is a first power supply and a second power supply. The first power supply and the second power supply are each narrow-banded. A digital predistorter is coupled to provide separate bands of a modulation signal for respective input of a first band of the bands to the first power supply and a second band of the bands to the second power supply. The first power supply generates a first power at a first center frequency. The second power supply generates a second power at least at a second center frequency spaced apart from the first center frequency for a wide-band configuration. The second power output from the second power supply is coupled to the first power output from the first power supply to provide a multiband power modulation output.

Abstract: A method, computer-readable medium and apparatus for creating a platform-specific logic design from an input design are disclosed. For example, a method includes receiving an input design and an identification of a target device. The method next determines an unconnected external interface of the input design and detects an unconnected external interface of the target device. The method then generates an updated design from the input design. The updated design includes the input design and further includes a connection between the unconnected external interface of the input design and the unconnected external interface of the target device.

Abstract: An embodiment of an apparatus for nonlinearity compensation is disclosed. For an embodiment, a pre-distorter is coupled to receive a first signal. The pre-distorter is configured to convert first values of the first signal into second values for a second signal. The pre-distorter includes a converter for converting the first values to the second values. A phase interpolator is coupled to receive the second signal. The second values are associated with nonlinearity of the phase interpolator. The phase interpolator is configured to provide an interpolated output from the second signal. The second signal is adjusted for the nonlinearity of the phase interpolator by use of the second values.

Abstract: An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.

Abstract: A programmable integrated circuit is disclosed. The programmable integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising configurable blocks; and a routing network coupled to each circuit block of the plurality of circuit blocks, the routing network enabling asynchronous data communication with the plurality of circuit blocks. Each circuit block comprises an interface portion having routing circuits coupled to the routing network, the routing circuits enabling routing data to the configurable blocks of the circuit block. A method of asynchronously routing data in a circuit block of an integrated circuit is also disclosed.

Abstract: A multi-port memory cell is disclosed that includes first and second cross-coupled inverter circuits. The input node of each inverter circuit is coupled to the output node of the other inverter circuit to receive the inverted output of the other inverter circuit. The multi-port memory cell includes a first pair of access transistors of a first type, each coupled to the input node of a respective one of the first and second inverter circuits. The multi-port memory cell also includes a second pair of access transistors of the second type, each coupled to the input of a respective one of the first and second inverter circuits. The multi-port cell exhibits advantages in layout compactness and SEU tolerance.

Abstract: A method of enabling detection of tampering with data provided to a programmable integrated circuit is described. The method comprises modifying a portion of the data to establish randomness in the data; and inserting, by a computer, a redundancy check value in the portion, wherein the redundancy check value is based upon the modified portion of the data. A programmable integrated circuit is also described.

Abstract: A method for removing bumps from incomplete interposer die(s) and/or defective interposer die(s) of an interposer wafer is described. The method includes forming bumps on an interposer wafer; identifying at least one incomplete interposer die and/or at least one defective interposer die of the interposer wafer; and removing bumps from the at least one incomplete interposer die and/or the at least one defective interposer die of the interposer wafer.

Abstract: A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier.

Abstract: In an approach for calibrating a delay line having a plurality of taps, a first clock signal is input to the delay line. A second clock signal is input to a reference circuit having a plurality of taps. In response to determining that output signals of selected taps of the delay line and reference circuit do not align, a next tap of the reference circuit is selected, to determine whether or not the output signals align. In response to determining that the output signals align, reference tap data indicative of the current reference tap is stored in association with a delay tap number of the current delay tap. A next tap of the delay line is selected to determine whether or not the output signals align.

Abstract: An embodiment of a method for a multiple-antenna receiver is disclosed. For this embodiment of the method, a detector obtains a channel matrix and a symbol vector. Contents of the channel matrix and the symbol vector are accessed in order and out of order, where the out of order access of the contents of the channel matrix and the symbol vector respectively provide a reordered channel matrix and a reordered symbol vector. The channel matrix is decomposed with the symbol vector to obtain first decomposition inputs. The reordered channel matrix is decomposed with the reordered symbol vector to obtain second decomposition inputs. The first decomposition inputs are sphere detected to provide first candidates. The second decomposition inputs are sphere detected to provide second candidates. Reliability information is generated from the first candidates and the second candidates.