Patents Assigned to Xilinx, Inc.
  • Calibration of a switching instant of a switch
    Patent number: 8890730
    Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventors: Donnacha Lowney, Christophe Erdmann, Edward Cullen
  • Apparatus and method for reducing plasma-induced damage in pMOSFETS
    Patent number: 8890164
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) for an integrated circuit includes a substrate of a first conductivity type, a first well region of a second conductivity type located in the substrate, and a second well region of the second conductivity type located within the substrate. The second well region is functionally connected to the first well region, and the second well region has a surface area greater than a surface area of the first well region. The MOSFET further includes a source of the first conductivity type located in the first well region, a drain of the first conductivity type located in the first well region, a substrate terminal of the second conductivity type located in the first well region, a gate oxide on a top surface of the first well region, and a gate electrode located on a top surface of the gate oxide.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventors: Hong-Tsz Pan, Qi Lin, Yun Wu, Bang-Thu Nguyen
  • Method and apparatus for dynamically aligning high-speed signals in an integrated circuit
    Patent number: 8890571
    Abstract: A method and apparatus for aligning an input signal to a clock signal in an integrated circuit are disclosed. The method includes receiving an input signal; determining whether the input signal is arriving too early or too late via a plurality of delay lines; and adjusting a delay of the plurality of delay lines in accordance with a result of the determining.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventor: John G. O'Dwyer
  • At-speed testing of multi-die integrated circuits
    Patent number: 8890562
    Abstract: An integrated circuit (IC) structure can include an interposer including a plurality of inter-die wires and a first die coupled to the interposer. The first die can include a first output including a first flip-flop coupled to a first inter-die wire of the plurality of inter-die wires and a first input including a second flip-flop coupled to a second inter-die wire of the plurality of inter-die wires. The IC structure can include a second die coupled to the interposer. The second die can be configured with a first circuit design forming circuitry that couples the first inter-die wire to the second inter-die wire.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventor: Ismed D. Hartanto
  • Methods of pipelining a data path in an integrated circuit
    Patent number: 8893071
    Abstract: A method of pipelining a data path in an integrated circuit is described. The method comprises receiving a circuit design to be implemented in the integrated circuit device; providing a placement of the circuit design in the integrated circuit device; identifying a most critical path of the placement; adding pipeline registers to the most critical path; and adding pipeline registers to all paths that are parallel to the most critical path. A computer program product for pipelining a data path in an integrated circuit is also described.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventor: Brian C. Gaide
  • Detection of power analysis attacks
    Patent number: 8892903
    Abstract: A circuit for detecting power analysis attacks includes at least one load circuit, a power supply line, and a switch coupled to the load circuit and to the power supply line. The switch is configured to enable and disable the at least one load circuit, and a voltage monitor is configured to sample voltage levels of the supply voltage. A detection circuit is coupled to the switch and to the voltage monitor. The detection circuit is configured to generate control signals for enabling and disabling the at least one load circuit, compare a first voltage level sampled when the at least one load circuit is disabled to a second voltage level sampled when the at least one load circuit is enabled, and generate an attack-detection signal in response to a difference between the sampled first voltage level and the sampled second voltage level being greater than a threshold voltage level.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Computing system with network attached processors
    Patent number: 8885334
    Abstract: A processor module can include a circuit board, a first programmable circuitry coupled to the circuit board, wherein the first programmable circuitry is configurable to implement different physical circuits, and a processor configured to execute program code. The processor can be coupled to the circuit board and to the first programmable circuitry. The processor module also can include random access memory (RAM) devices coupled to the circuit board and electrically coupled to the first programmable circuitry. The RAM devices can be coupled to the first programmable circuitry to form parallel channels of the RAM devices. The processor module further can include an interface coupled to the circuit board and electrically coupled to the first programmable circuitry for coupling input and output between the first programmable circuitry and external circuitry.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: November 11, 2014
    Assignee: Xilinx, Inc.
    Inventor: Glenn A. Baxter
  • Reducing variation in multi-die integrated circuits
    Patent number: 8886481
    Abstract: A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: November 11, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arifur Rahman, Michael J. Hart, Venkatesan Murali
  • Time-to-digital conversion
    Patent number: 8884804
    Abstract: An apparatus relating generally to time-to-digital conversion is disclosed. In this apparatus, a time-to-digital converter is coupled to a period sensor. The period sensor includes a pulse generator to generate a pulse. An integrator of the period sensor is coupled to receive the pulse to generate an analog voltage signal responsive to the pulse. The time-to-digital converter includes an analog-to-digital converter coupled to provide a digital signal associated with the analog voltage signal.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Xilinx, Inc.
    Inventors: Amitava Majumdar, Siva Charan Nimmagadda, Baanurathan Sadasivam, Richard W. Swanson, Yohan Frans
  • Cell-level electrostatic discharge protection for an integrated circuit
    Patent number: 8881085
    Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: November 4, 2014
    Assignee: Xilinx, Inc.
    Inventors: James Karp, Greg W. Starr, Mohammed Fakhruddin
  • Dataflow parameter estimation for a design
    Patent number: 8881079
    Abstract: An embodiment of a method of high-level synthesis of a dataflow pipeline is disclosed. This embodiment includes obtaining processes from the high-level synthesis of the dataflow pipeline. A schedule for read operations and write operations for first-in, first-out data channels of the processes is determined. A dataflow through the dataflow pipeline for the schedule is determined. An edge-weighted directed acyclic graph for the processes and the dataflow is generated. A longest path in the edge-weighted directed acyclic graph is located. A weight for the longest path is output as an estimate, such as a latency estimate for example, for the dataflow.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 4, 2014
    Assignee: Xilinx, Inc.
    Inventors: Peichen Pan, Chang'an Ye, Kecheng Hao
  • Integrated circuit structure having a capacitor structured to reduce dishing of metal layers
    Patent number: 8878337
    Abstract: A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 4, 2014
    Assignee: Xilinx, Inc.
    Inventors: Hong-Tsz Pan, Yun Wu, Shuxian Wu, Qi Lin, Bang-Thu Nguyen
  • Characterizing dies
    Patent number: 8872536
    Abstract: An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Babak Ehteshami
  • Generation of internal interfaces for a block-based design
    Patent number: 8875073
    Abstract: A method relating generally to computer aided design is disclosed. In such method, a block-based model of a hardware realizable system is obtained. An internal gateway-in and an internal gateway-out of a module of the block-based model are identified. An interface protocol is assigned for the internal gateway-in and the internal gateway-out. Data type and data propagation for the module at the internal gateway-in and the internal gateway-out are analyzed. The internal gateway-in and the gateway-out are transformed into an input/output interface. Integrated code is generated for subsequent realization of the input/output interface in hardware.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Jinsong Du
  • Pulse width determination for phase detection
    Patent number: 8874999
    Abstract: An embodiment of an apparatus includes a detector to receive a first input signal and a second input signal to provide a first error signal and a second error signal. A pulse width determination block receives the first and second error signals, as well as a digital oscillating signal, to output a first pulse width value and a second pulse width value, respectively. A pulse width accumulator accumulates the first and second pulse width values responsive to at least one cycle of the digital oscillating signal to provide a first accumulated value and a second accumulated value. An error generator provides an error value as a difference between the first accumulated value and the second accumulated value. The error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: David F. Taylor, Matthew H. Klein, Vincent Vendramini
  • Circuitry for parallel decoding of data blocks
    Patent number: 8875001
    Abstract: In one embodiment, a Chien search circuit includes a plurality of evaluation circuits, each configured to sequentially evaluate possible roots ?i in a respective subset of possible roots of an error location polynomial (?(x)). Each evaluation circuit includes a respective sub-circuit for each of a plurality of coefficients ?i (0?i?T) of the error location polynomial ?(x) having T+1 coefficients. Each sub-circuit is configured to calculate one term of the error location polynomial for each possible root ?i in the respective subset of possible roots. Each evaluation circuit is configured to evaluate the error location polynomial for each possible root in the respective subset of possible roots, as a sum of the terms calculated by the plurality of sub-circuits.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Raied N. Mazahreh, Hai-Jo Tarn
  • On chip performance tracking for a system on a chip
    Patent number: 8874801
    Abstract: An integrated circuit includes a bus (905), processor coupled to the bus (910), a peripheral coupled to the bus (930), and a performance tracking module (215) configured to detect bus events and non-bus related events. The performance tracking module is configured to determine a bus performance metric from the bus events and a non-bus performance metric from the non-bus related events.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Nagalatha Ramineni, Sesibhushana Rao Bommana
  • Embedded memory and dedicated processor structure within an integrated circuit
    Patent number: 8874837
    Abstract: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Christopher E. Neely, Gordon J. Brebner
  • SEMICONDUCTOR PACKAGE HAVING IC DICE AND VOLTAGE TUNERS
    Publication number: 20140312483
    Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: Xilinx, Inc.
    Inventor: Xilinx, Inc.
  • Circuit enabling and a method of generating a product in a decoder circuit
    Patent number: 8869013
    Abstract: A circuit enabling generating a product in a decoder circuit is disclosed. The circuit comprises a first memory element coupled to receive a first error value and a first portion of a second error value; a second memory element coupled to receive the first error value and a second portion of the second error value; and an adder circuit coupled to add an output of the first memory element and an output of the second memory element. The output of the first memory element is generated in response to an address based on the first error value and the first portion of the second error value, and the output of the second memory element is generated in response to an address based on the first error value and the second portion of the second error value. A method for generating a product in a decoder circuit is also disclosed.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: October 21, 2014
    Assignee: Xilinx, Inc.
    Inventor: Ben J. Jones