Patents Assigned to Xilinx, Inc.
  • Semiconductor structure for an electrostatic discharge protection circuit
    Patent number: 8866229
    Abstract: An embodiment of a semiconductor structure for an electrostatic discharge (“ESD”) protection circuit is disclosed. For this embodiment, there is a substrate of a first polarity type. A device area of the substrate has a source region and a drain region of a transistor. The device area is of the first polarity type, and the source region and the drain region are each of a second polarity type. A well region of the second polarity type surrounds the device area. An outer tap of the first polarity type surrounds the well region, and a bridge interconnects the source region and the outer tap.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: October 21, 2014
    Assignee: Xilinx, Inc.
    Inventors: Mohammed Fakhruddin, James Karp
  • Oversized interposer formed from a multi-pattern region mask
    Patent number: 8869088
    Abstract: An embodiment of an interposer is disclosed. In such an embodiment, there is a first printed circuit region and a second printed circuit region. The second printed circuit region is proximate to the first printed circuit region with a seam region between the first printed circuit region and the second printed circuit region. The seam region includes a first die seal and a second die seal spaced apart from one another with a scribe line located between the first die seal and the second die seal.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Xilinx, Inc.
    Inventor: Rafael C. Camarota
  • Verification and debugging using heterogeneous simulation models
    Patent number: 8868396
    Abstract: A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: October 21, 2014
    Assignee: Xilinx, Inc.
    Inventors: Nabeel Shirazi, L. James Hwang, Chi Bun Chan, Hem C. Neema, Kumar Deepak
  • Flip-flop array with option to ignore control signals
    Patent number: 8866509
    Abstract: Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Xilinx, Inc.
    Inventors: Robert I. Fu, Chi M. Nguyen, James M. Simkins, Brian C. Gaide, Brian D. Philoksky
  • Methods of authenticating a programmable integrated circuit in combination with a non-volatile memory device
    Patent number: 8863230
    Abstract: Methods of authenticating a combination of a programmable IC and a non-volatile memory device, where the non-volatile memory device stores a configuration data stream implementing a user design in the programmable IC. A first identifier unique to the programmable IC is stored in non-volatile memory in the programmable IC. A second identifier unique to the non-volatile memory device is stored in the non-volatile memory device. As part of the process in which the configuration data stream is used to program the programmable IC with the user design, a function is performed on the two identifiers, producing a key specific to the programmable IC/non-volatile memory device combination. The key is then compared to an expected value. When the key matches the expected value, the user design is enabled. When the key does not match the expected value, at least a portion of the user design is disabled.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: October 14, 2014
    Assignee: Xilinx, Inc.
    Inventors: Steven K. Knapp, James A. Walstrum, Jr., Shalin Umesh Sheth
  • Inductor structure with a current return encompassing a coil
    Patent number: 8860180
    Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 14, 2014
    Assignee: Xilinx, Inc.
    Inventors: Jing Jing, Shuxian Wu, Parag Upadhyaya
  • Circuit for forward error correction encoding of data blocks
    Patent number: 8862968
    Abstract: In one embodiment, an encoder circuit is provided. The encoder includes an input circuit having a plurality of finite field subtraction circuits, each configured to receive a respective one of the sequence of symbols and subtract the symbol from a respective symbol of an intermediate polynomial to produce a respective feedback symbol. For each coefficient of a code generation polynomial, a first circuit is configured to multiply each feedback symbol by a respective constant corresponding to the coefficient to produce a first set of intermediate results. Each first set of intermediate results is summed to produce a second intermediate result. A buffer circuit of the encoder is configured and arranged to store the second intermediate results produced by the first circuit as the intermediate polynomial.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: October 14, 2014
    Assignee: Xilinx, Inc.
    Inventor: Graham Johnston
  • Recursion unit scheduling
    Patent number: 8848842
    Abstract: An embodiment of a decoder is disclosed. For this embodiment of the decoder, a first estimation unit and a second estimation unit are for iterative decoding. A scheduler is to receive a mode select signal to provide either an indication of first scheduling information or second scheduling information to the first estimation unit and the second estimation unit responsive to the mode select signal.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Xilinx, Inc.
    Inventor: Christopher H. Dick
  • Back annotation of output time delays
    Patent number: 8850377
    Abstract: A method of configuring an integrated circuit includes developing a circuit simulation model of a circuit having an output port to be configured in the integrated circuit. A number of simultaneously switched outputs (SSOs) are defined according to the circuit simulation model, and a propagation delay at the output port is characterized according to the number of SSOs. The circuit simulation model is back-annotated from the output port to add the propagation delay in a signal path of the output port to produce a second circuit simulation model. A configuration bitstream is generated according to the second circuit simulation model and the integrated circuit is configured according to the bitstream.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Xilinx, Inc.
    Inventor: Jesse H. Jenkins, IV
  • Injection-controlled-locked phase-locked loop
    Patent number: 8841948
    Abstract: An apparatus relates generally to an injection-controlled-locked phase-locked loop (“ICL-PLL”) is disclosed. In this apparatus, a delay-locked loop is coupled to an injection-locked phase-locked loop. An injection-locked oscillator of the injection-locked phase-locked loop is in a feedback loop path of the delay-locked loop.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 23, 2014
    Assignee: Xilinx, Inc.
    Inventors: Jun-Chau Chien, Wayne Fang, Parag Upadhyaya, Jafar Savoj, Kun-Yung Chang
  • Circuit and method for multiplying a signed value by a constant
    Patent number: 8843541
    Abstract: A multiplier circuit and method multiply a signed value by a constant. The signed value received at an input port is separable into two or more splices. A first splice is a most significant one of the splices, and a second splice is another one of the splices. One or more memories provide respective partial products for the splices, and these memories include a shared memory. The shared memory provides the respective partial products for the first and second splices from storage locations in the shared memory. The storage locations that are readable to provide the respective partial product for the second splice are a subset of the storage locations that are readable to provide the respective partial product for the first splice. An addition circuit sums the respective partial products for the splices.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: September 23, 2014
    Assignee: Xilinx, Inc.
    Inventor: Gordon I. Old
  • Circular pipeline processing system
    Patent number: 8843807
    Abstract: In one embodiment, a circular pipeline processing system is provided. The system includes a plurality of processing stages configured to operate in a circular pipeline. Each processing stage is configured to output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in a memory buffer of the processing stage. Each processing stage is configured to select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on one or more of availability of memory sufficient for storage of an unprocessed data block or availability of a partially processed data block. The processing stage is configured to process the selected data block.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: September 23, 2014
    Assignee: Xilinx, Inc.
    Inventors: Colin Stirling, David I. Lawrie, David Andrews
  • Semiconductor structure and method for interconnection of integrated circuits
    Patent number: 8841752
    Abstract: In one or more embodiments, a semiconductor structure is provided that includes a plurality of interposer dice on an un-singulated segment of a semiconductor wafer. Scribe lanes circumscribing each of the plurality of interposer dice have widths of at least 2.5% of the width of each interposer die. Each interposer die includes a first contact array formed on a first side of the interposer die, a plurality of vias formed through the interposer die, one or more wiring layers formed on the first side of the interposer die and electrically coupling the first contact array to the plurality of vias, and a second contact array formed on a second side of the interposer die and electrically coupled to the plurality of vias.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: September 23, 2014
    Assignee: Xilinx, Inc.
    Inventors: Raghunandan Chaware, Kumar Nagarajan
  • Resistor network implemented in an integrated circuit
    Patent number: 8842034
    Abstract: A resistor network implemented in an integrated circuit includes a first plurality of interconnect traces coupled in series at a first plurality of nodes; a first plurality of switches coupled between the first plurality of nodes and an output node; a second plurality of interconnect traces coupled in series at a second plurality of nodes; and a second plurality of switches coupled between the second plurality of nodes and the output node, wherein a voltage at the output node is generated in response to a resistance of the resistor network based upon a configuration of the first plurality of switches and the second plurality of switches.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: September 23, 2014
    Assignee: Xilinx, Inc.
    Inventor: Jingfeng Gong
  • TIMESTAMP CORRECTION IN A MULTI-LANE COMMUNICATION LINK WITH SKEW
    Publication number: 20140269769
    Abstract: A method, non-transitory computer readable medium and apparatus for correcting a timestamp in a multi-lane communication link with a skew are disclosed. For example, the method receives a data packet, a time stamp for the data packet and a fill level for a lane of the multi-lane communication link carrying the data packet, calculates a corrected timestamp for the data packet and replaces the time stamp for the data packet with the corrected timestamp.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: XILINX, INC.
    Inventor: Xilinx, Inc.
  • CIRCUITS FOR AND METHODS OF IMPLEMENTING A GAIN STAGE IN AN INTEGRATED CIRCUIT
    Publication number: 20140266434
    Abstract: A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Xilinx, Inc.
    Inventor: Xilinx, Inc.
  • MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT
    Publication number: 20140281844
    Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Xilinx, Inc.
    Inventor: Xilinx, Inc.
  • ANALOG BLOCK AND TEST BLOCKS FOR TESTING THEREOF
    Publication number: 20140281716
    Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: Xilinx, Inc.
    Inventor: Xilinx, Inc.
  • MULTI-BOOT OR FALLBACK BOOT OF A SYSTEM-ON-CHIP USING A FILE-BASED BOOT DEVICE
    Publication number: 20140281455
    Abstract: A method includes initiating a boot of a system-on-chip coupled to a boot device. The boot is initiated from boot code stored in nonvolatile memory responsive to a power-on-reset. Under control of the boot code: a first register value is loaded into a register; a name string from the boot code is accessed; the first register value is obtained from the register; and the first register value and name string are converted to a first string value, which is provided as a first filename. The boot device is searched for a boot image file with the first filename. If the first filename is not found in the boot device, the first register value is incremented to provide a second register value. The obtaining, converting, and searching are repeated using a second filename generated using the second register value, and a valid filename for the boot image file is iteratively generated.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: XILINX, INC.
    Inventor: Xilinx, Inc.
  • MULTI-LAYER CORE ORGANIC PACKAGE SUBSTRATE
    Publication number: 20140262440
    Abstract: A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: XILINX, INC.
    Inventor: Xilinx, Inc.