Patents Assigned to Xilinx, Inc.
  • CALIBRATION OF A SWITCHING INSTANT OF A SWITCH
    Publication number: 20140266824
    Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: XILINX, INC.
    Inventor: XILINX, INC.
  • Mixed-language simulation
    Patent number: 8838431
    Abstract: In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventors: Valeria Mihalache, Hem C. Neema, Kumar Deepak, Sonal Santan
  • Systems and methods for configuring a switch
    Patent number: 8836409
    Abstract: An apparatus includes: a switch having a first transistor, the first transistor having a gate, wherein the switch is connected between a first pad and a second pad; and a first biasing circuit coupled to the gate of the first transistor, wherein the first biasing circuit is configured for outputting a first voltage, the first voltage being the lowest one of (1) a voltage of the first pad, (2) a voltage of the second pad, and (3) a ground voltage; wherein the gate of the first transistor is driven by the first voltage from the first biasing circuit in response to an enable signal being set for configuring the switch to be off.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventors: Edward Cullen, April M. Graham, Ionut C. Cical
  • Receiver circuit
    Patent number: 8838056
    Abstract: A receiver circuit includes an analog front-end circuit, a first adaptation circuit, and a second adaptation circuit. A method operates the receiver circuit. The analog front-end circuit is configured to resolve an output signal from an input signal as a function of adjustable parameters. The first adaptation circuit is coupled to the analog front-end circuit and is configured to determine values of the adjustable parameters responsive to the output signal. The second adaptation circuit is coupled to the analog front-end circuit and to the first adaptation circuit. The second adaptation circuit is configured to adjust the values of the adjustable parameters responsive to one or more operating conditions of the receiver circuit. These operating conditions include a temperature and/or a power supply voltage of the receiver circuit.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventors: Mustansir Fanaswalla, Khaldoon S. Abugharbieh, David L. Ferguson
  • Systems and methods for digital processing based on active signal channels of a communication system
    Patent number: 8837633
    Abstract: A communication system includes digital signals that carry data and correspond to channels of a composite signal to be transmitted across a communication channel. Active channels are detected and used to configure digital processing. In one embodiment, active channels are detected, where a particular active channel corresponds to the presence of a particular one of the digital signals. Active channel detection may be used to configure pre-distortion of a composite signal to be transmitted to compensate for distortion in a digital-to-analog converter. Likewise, active channel detection may be used to optimize the configuration of an up-converter. In one embodiment, a programmable device is configured based on detected active channels into a plurality of different configurations.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventor: Christopher H. Dick
  • Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows
    Patent number: 8839166
    Abstract: A method, non-transitory computer readable medium and apparatus for using an out-of-context sub-block in a hierarchical design flow for an integrated circuit are disclosed. For example, the method identifies one or more sub-blocks in the hierarchical design flow that are eligible for creating the out-of-context sub-block, receives a selection of one of the one or more sub-blocks that are eligible and creates the out-of-context sub-block for the one of the one or more sub-blocks that is selected.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventors: Sudipto Chakraborty, David A. Knol, Stephen P. Rozum, Ryan A. Linderman, Derrick S. Woods
  • Multi-protocol data bus interface
    Patent number: 8838869
    Abstract: In one embodiment, a multi-protocol communication circuit is provided. The communication circuit includes a plurality of protocol bridge circuits, each configured to convert data between a first format and a respective second format corresponding to a respective communication protocol. A switch network provides routable connections between the protocol bridge circuits and one or more interface circuits. Each interface circuit is configured to convert data between the first format and a raw data format. Due to the common first format, an interface circuit may be configured for select ones of different communication protocols by routing data in the first format between the interface circuit and a protocol bridge circuit corresponding to the select one of the different communication protocols.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventor: Kiran S. Puranik
  • Plesiochronous clock generation for parallel wireline transceivers
    Patent number: 8836391
    Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventors: Parag Upadhyaya, Jafar Savoj, Anthony Torza
  • INTEGRATED CIRCUIT DEVICES HAVING MEMORY AND METHODS OF IMPLEMENTING MEMORY IN AN INTEGRATED CIRCUIT DEVICE
    Publication number: 20140254232
    Abstract: An integrated circuit device having memory is disclosed. The integrated circuit device comprises programmable resources; programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling a communication of signals with the programmable resources; a plurality of memory blocks; and dedicated interconnect elements coupled to the plurality of memory blocks, the dedicated interconnect elements enabling access to the plurality of memory blocks. A method of implementing memory in an integrated circuit device is also disclosed.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: XILINX, INC.
    Inventor: Xilinx, Inc.
  • PACKAGE INTEGRITY MONITOR WITH SACRIFICIAL BUMPS
    Publication number: 20140253171
    Abstract: An apparatus with package integrity monitoring capability, includes: a package having a die connected to an interposer through a plurality of bumps, wherein at least some of the bumps comprise dummy bumps; a package integrity monitor having a transmitter to transmit a test signal and a receiver to receive the test signal; and a first scan chain comprising a plurality of alternating interconnects in the die and in the interposer connecting some of the dummy bumps in series, wherein the first scan chain has a first end coupled to the transmitter of the package integrity monitor and a second end coupled to the receiver of the package integrity monitor.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: XILINX, INC.
    Inventor: XILINX, INC.
  • SUBSTRATE-LESS INTERPOSER TECHNOLOGY FOR A STACKED SILICON INTERCONNECT TECHNOLOGY (SSIT) PRODUCT
    Publication number: 20140252599
    Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: XILINX, INC.
    Inventor: Xilinx, Inc.
  • Peak-to-average power ratio reduction with bounded error vector magnitude
    Patent number: 8831117
    Abstract: Method and apparatus for signal processing to minimize the peak to average power ratio of an Orthogonal Frequency Division Multiplexing (“OFDM”) or Orthogonal Frequency Division Multiple Access (“OFDMA”) signal with bounded error vector magnitude for an integrated circuit are described. An Active Constellation Extension (“ACE”) iteration, using a constellation points adjustment module, is performed. Symbols outside of a bounded region after the ACE iteration are identified. The bounded region is determined responsive to an error vector magnitude target. The symbols identified are translated to the bounded region.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventors: Raghavendar M. Rao, Christopher H. Dick
  • Method of and circuit for generating a spread spectrum clock signal
    Patent number: 8831064
    Abstract: A method of generating a spread spectrum clock signal in an integrated circuit, the method comprising providing a programmable digital clock generator in programmable logic of the integrated circuit, coupling a user-programmable control signal to the programmable clock generator to control the frequency deviation of the spread spectrum clock signal, and generating the spread spectrum clock signal in response to the user-programmable control signal.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventor: Alireza S. Kaviani
  • Optimal FPGA based hadamard detection
    Patent number: 8832172
    Abstract: A configuration for FPGA logic is provided to perform random access channel (RACH) preamble detection used in 3G mobile communications to identify individual rows of a Hadamard matrix using a Walsh Hadamard Transform (WHT). The configuration provides minimal add/subtract circuit blocks for the WHT by using stages, each stage containing a shift register connected to an add/subtract circuit. The shift register has outputs provided from a tap into its nth and n/2 elements, the outputs being connected to an add/subtract circuit, wherein n is the order of the Hadamard matrix. In a further embodiment parallel connected shift registers are used in each stage to increase operation speed.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventors: Neil Lilliott, Andrew David Laney
  • Bias voltage control for an output driver
    Patent number: 8829983
    Abstract: An embodiment of an apparatus is disclosed. For this embodiment, an output driver and a bias voltage controller are included. The bias voltage controller is coupled to provide first and second bias voltages to the output driver. The bias voltage controller comprises a bias generator coupled to a first voltage supply, a second voltage supply, and a ground node. The bias generator has a first bias node for sourcing the first bias voltage. The first voltage supply is configured to provide a higher voltage level than the second voltage supply. A resistor-divider network is coupled to the first voltage supply and the ground node. A watch dog circuit is coupled to the resistor-divider network, bias generator, and the ground node. A comparison circuit is coupled to the bias generator and the second voltage supply. The comparison circuit has a second bias node for sourcing the second bias voltage.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventor: Krishna Chaitanya Potluri
  • Protecting against differential power analysis attacks on sensitive data
    Patent number: 8832462
    Abstract: An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the first quantity of the random data, the operation is performed with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the input data, the operation is performed with the sensitive data on a second quantity of random data using the circuit arrangement.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Time skew extraction of interleaved analog-to-digital converters
    Patent number: 8830094
    Abstract: An exemplary integrated circuit for performing time skew extraction includes a first subtractor, an array of subtractors separate from the first subtractor, and an array of averaging circuits. Inputs of the first subtractor are coupled to outputs of a plurality of channels of an interleaved analog-to-digital-converter and computes distances between samples of a signal that are measured consecutively by pairs of channels in the plurality of channels. At least some averaging circuits in the array of averaging circuits compute an average of those of the distances that correspond to a respective one of the pairs of channels; one averaging circuit in the array of averaging circuits computes an average of all of the distances. Each subtractor in the array of subtractors computes a difference between an average computed by one of the at least some of the averaging circuits and the average of all of the distances.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventor: Christophe Erdmann
  • Circuit and method for ordering data words
    Patent number: 8832326
    Abstract: Quick key-based ordering of data words is provided. A memory is arranged to receive the keys at an address input port. The memory is adapted to provide at a data output port one of a plurality of ordered sets of identifiers. Each key is associated with a respective one of the data words and each identifier of the one of the ordered sets identifies a respective one of the data words. Each of a plurality of multiplexers is arranged to receive a respective identifier of the one of the ordered sets from the memory and to receive the data words. Each multiplexer is adapted to select the respective one of the data words identified by the respective identifier. A program storage medium may be configured with instructions to perform operations including generating configuration data for a programmable device. The configuration data may implement the memory and the multiplexers.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventor: Thomas E. Fischaber
  • Integrated circuit with power gating
    Patent number: 8823405
    Abstract: An integrated circuit has a first independent power domain having a first power domain bus electrically connected to first functional blocks and a first power pad electrically connected to the first power domain bus and a second independent power domain having a second power domain bus electrically connected to second functional blocks and a second power pad electrically connected to the second power domain bus. A test element is between the first power domain bus and the second power domain bus.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: September 2, 2014
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Interposer having an inductor
    Patent number: 8823133
    Abstract: An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: September 2, 2014
    Assignee: Xilinx, Inc.
    Inventors: Michael O. Jenkins, James Karp, Vassili Kireev, Ephrem C. Wu