Abstract: Up-binning a circuit design includes receiving a first bitstream specifying the circuit design. The circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit. Using a processor, a first parameter of the first bitstream is determined. The first parameter is applied to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design. A timing analysis is performed upon the parameterized hardware netlist. The process further includes determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit. The second speed grade is slower than the first speed grade.

Abstract: An embodiment of a technique to determine an expected occurrence of a signal is disclosed. The technique includes receiving first and second signals, and storing delay information representing an expected time delay from an occurrence of the first signal to a point in time corresponding approximately to an expected occurrence of the second signal. The technique further includes responding to an occurrence of the first signal by: waiting for a time interval equivalent to the expected time delay, evaluating the second signal at approximately the end of the time interval, and adjusting the stored delay information if the second signal occurred outside a time window associated with the end of the time interval.

Abstract: An interconnect array is described. The interconnect array comprises a pattern of adjacent interconnect tiles, each interconnect tile comprising ten interconnect locations including eight I/O signal connectivity locations forming a perimeter array having a corner I/O signal connectivity location, a center connectivity location surrounded by the eight I/O signal connectivity locations in the perimeter array being a first ground connectivity location or a power connectivity location, and a second ground connectivity location adjacent to the corner I/O signal connectivity location of the perimeter array and externally offset from the perimeter array to form an asymmetrically shaped interconnect tile. At least one interconnect tile of the pattern of adjacent interconnect tiles has a center connectivity location that is a power connectivity location.

Abstract: Methods and circuits detect a burst error in a block of data bits. Coset calculator circuits calculate coset leaders from a syndrome generated from the data bits of the block. The coset calculator circuits calculate the coset leaders for each frame of the data bits. For each frame, comparator circuits input a corresponding coset leader of the coset leaders. Each comparator circuit determines, for each burst-length portion of one or more burst-length portions within the corresponding coset leader, whether the coset bits of the corresponding coset leader are zero except for the coset bits within the burst-length portion. An error-locator circuit outputs an error vector describing the burst error in the block in response to one of the comparator circuits determining that the coset bits of the corresponding coset leader are zero except for the coset bits within one of the burst-length portions within the corresponding coset leader.

Abstract: An integrated circuit structure can include a silicon interposer. The silicon interposer can include a first elliptical TSV and a keep out zone (KOZ) for stress effects upon active devices surrounding the first elliptical TSV. A size of the KOZ can be determined by a transverse diameter and a conjugate diameter of the first elliptical TSV.

Abstract: A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract: A computer implemented method for designing a circuit includes associating a high level design constraint with a first high level circuit component of a high level circuit design within a high level modeling system and translating the high level circuit design into a low level circuit design comprising at least one low level circuit component derived from the first high level circuit component. The method also includes automatically generating at least one low level design constraint from the high level design constraint for at least one low level circuit component and storing each low level design constraint in association with the low level circuit design.

Abstract: A system for wide frequency range clock generation, includes: a phase lock loop (PLL) to generate a signal having a frequency; at least one fractional-N divider to divide the frequency of the signal; and a multiplexer to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal.

Abstract: A method and apparatus for efficient drive level selection for, e.g., power amplifiers utilized within a wireless communication system, which utilizes digital predistortion (DPD) to adaptively and predictively select drive level. The DPD, e.g., increases the power amplifier's efficiency while maintaining spectral mask compliance within the designated frequency band of transmission. The method first determines a peak amplitude of an undistorted waveform that is to be transmitted and then predicts the maximum power that is to be transmitted by the power amplifier after the undistorted signal has been predistorted. An over-drive metric is then calculated based upon the predicted drive level of the power amplifier, which indicates whether or not the cascade of the predistorter and the power amplifier is predicted to operate linearly. The over-drive metric may then be used to ensure optimal power amplifier performance, thereby eliminating the need to use overly conservative power amplifier drive settings.

Abstract: A method of and apparatus for synchronous data transfer are described. The method may include encoding a clock period and data into an encoded signal, transmitting the encoded signal from a master device to a slave device, and recovering the data at the slave device without using a local oscillator. The apparatus may comprise a first integrated circuit including a master device configured to transmit an encoded signal of a clock period and data on a first port, and a second integrated circuit including a slave device where the slave device is configured to receive the encoded signal on a second port coupled to the first port and to recover the data without using a local oscillator.

Abstract: A circuit includes a first input terminal, a first transmission line, a first sampling switch coupled to the first input terminal through the first transmission line, a first sampling capacitor coupled to the sampling switch, and a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength stub configured to reduce kickback noise on the first transmission line. A method for reducing kickback noise in a circuit includes determining a frequency associated with a kickback noise on a first transmission line of the circuit, the circuit having an input terminal coupled to the first transmission line, configuring a length of an open-circuit quarter wavelength stub to correspond to the determined frequency, and coupling the open-circuit quarter wavelength stub to the first transmission line to filter the frequency associated with the kickback noise.

Abstract: An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract: A method of performing digital pre-distortion in a communication network is described. The method comprises implementing a transceiver in the communication network, the transceiver enabling the transfer of communication signals in the communication network by way of a wireless communication channel; sampling signals, at the transceiver, associated with a transmit signal which are necessary to perform digital pre-distortion; providing the sampled signals to a remote computer; and generating, at the remote computer, parameters to be applied to a digital pre-distortion circuit of the transceiver. A communication network configured to enable digital pre-distortion is also described.

Abstract: A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.

Abstract: A driver circuit of an integrated circuit is described. The driver circuit comprises a signal node coupled to receive an output signal of the integrated circuit; an inductor circuit having a resistor coupled in series with an inductor between a first terminal and a second terminal, wherein the first terminal is coupled to the signal node; an electrostatic discharge protection circuit coupled to the second terminal of the inductor circuit; and an output node coupled to the second terminal of the inductor circuit. A method of generating an output signal is also disclosed.

Abstract: Approaches for placing and routing a circuit design on a programmable integrated circuit (IC) are disclosed. One partial reconfiguration (PR) resource portion of the circuit design is selected from a plurality of PR resource portions of the design. Uncontained resources in the PR resource portion is identified. The PR resource portion, less the uncontained resources, is placed in an assigned region, and the uncontained resources is placed on the programmable IC unconstrained by the assigned region of the PR resource portion. The design is routed from the placed PR resource portion to the placed uncontained resources, and the process is repeated for each unplaced PR resource portion. After placing the plurality of PR resource portions and routing to uncontained resources in the plurality of PR resource portions, unplaced portions of the circuit design are placed and routed.

Abstract: A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed.

Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.