Abstract: A memory cell (300) having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first transistor (306) of a first type is in a first well (334) of a second type having a first well tap (342). A second transistor (308) of the first type is in a second well (336) of the second type having a second well tap (344). A third transistor (310) of the second type is in a third well (338) of the first type having a third well tap (346); and a fourth transistor (312) of the second type is in a fourth well (340) of the first type having a fourth well tap (348). The first well, second well, third well, and forth well are isolated from each of the other wells.

Abstract: Circuits, systems, and methods for processing outlier pixels include a spatial filter and a temporal filter. The spatial filter is configured to compute a pixel difference for each pixel as a function of a pixel value of the pixel and pixel values of nearby pixels within each frame. The spatial filter is configured to dynamically add the pixel to a candidate list when the pixel difference exceeds a threshold value. The temporal filter dynamically removes a pixel from the candidate list when there is a divergence of a pixel value of the pixel in successive frames. The temporal filter determines a pixel in the candidate list is an outlier pixel when there is no such divergence in the successive frames.

Abstract: Processing a circuit design includes generating a transformation output from a transformation input for each of a plurality of transformations of a synthesis flow applied to the circuit design. For each transformation, the transformation input and the transformation output represent the circuit design. At least one circuit element is changed from the transformation input to the transformation output. For each transformation, a hardware description language representation of the transformation input and a hardware description language representation of the transformation output are generated. For each transformation, determining whether the hardware description language representation of the transformation input is equivalent to the hardware description language representation of the transformation output.

Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

Abstract: One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.

Abstract: A method of processing a signal within a receiver can include generating, using the receiver, a candidate list including at least one entry for a signal. Each entry can include a candidate symbol vector and an L1-Norm error metric. The method can include, for each entry, generating an L1-Norm transformation from the L1-Norm error metric, wherein the L1-Norm transformation depends upon a function of a number of receiving antennas of the receiver. The signal can be decoded using the candidate list including the L1-Norm transformations.

Abstract: A Schmitt trigger inverter circuit can include a first inverter. The first inverter can include a first pull-up device, a first pull-down device and a second pull-down device. The first inverter can receive an input signal. The Schmitt trigger inverter circuit can include a second inverter coupled in series with the first inverter and including an output that generates an output signal. The Schmitt trigger inverter circuit further can include a switch coupled to the output of the second inverter circuit and that is selectively enabled by the output signal. The switch can couple a predetermined reference voltage to a source terminal of the first pull-down device when in an enabled state. Coupling the predetermined reference voltage to the source terminal of the first pull-down device can alter a threshold voltage of the Schmitt trigger inverter circuit.

Abstract: A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.

Abstract: A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.

Abstract: An analog-to-digital converter (ADC) includes an analog input stage including an output configured to generate an analog output signal and a digital stage coupled the output of the analog input stage. The digital stage is configured to classify the analog output signal into one of a plurality of consecutive voltage ranges. Responsive to the analog output signal being classified in a first enumerated voltage range of the plurality of voltage ranges during a rotation of a sample, a voltage for a subsequent rotation is determined as if the analog output signal is classified into a non-enumerated voltage range selected according to a state of a random number signal.

Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.

Abstract: An apparatus relating generally to an analog multiplexer is disclosed. In such an apparatus, the analog multiplexer has first select circuits and at least one second select circuit. The first select circuits have respective input nodes and output nodes. The output nodes are all coupled to one another to provide an output node of the analog multiplexer. The first select circuits are coupled to a first supply voltage of a first supply domain. The at least one second select circuit is coupled to a second supply voltage of a second supply domain different from the first supply domain. The at least one second select circuit has an input port and an output port. The output port is coupled to an input node of the input nodes.

Abstract: Processing a circuit design for implementation on a target device includes, for a first driver that is a driver of a net having a plurality of loads, selecting a second driver that is a driver of the first driver. A representation of a rectilinear Steiner arborescence (RSA) tree is generated from the second driver and the plurality of loads. The RSA tree includes nodes representative of the plurality of loads and a plurality of Steiner points. A subset of the plurality of Steiner points in the RSA tree is selected for disposing respective replicated instances of the first driver. The respective replicated instances of the first driver are assigned to locations on the target device associated with the subset of Steiner points. The connections from each of the respective replicated instances of the first driver are assigned to a respective subset of the plurality of loads.

Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.

Abstract: An apparatus consisting of a digital communication channel comprised of a multiplicity of lanes where data is striped across the lanes in a predefined sequence. Each lane has the ability to be powered down or powered up in response to the amount of data being held in a transmit buffer at one end of the communication channel. The method consists of monitoring the amount of data being held in the transmit buffer; making the decision of how many lanes are required based on the amount of data; sending signals to cause the required number of lanes to be powered down or powered up; and performing the required power down or power up action at the particular transmitter and receiver.

Abstract: According to an embodiment, an die for routing signals in a plurality of metal layers of an integrated circuit device is disclosed. The die comprises a first pair of conductive lines (302A and 302B) having a first reference line and a first signal line, the first reference line having traces and crossover segments in a plurality of metal layers; and second pair of conductive lines (304A and 304B) having a second reference line and a second signal line, the second reference line having traces and crossover segments in the plurality of metal layers which are offset from the traces and crossover segments of the first reference lines; wherein a first signal trace (310) of the first signal line in a first metal layer is adjacent to a first reference trace (308) of the first reference line on a first side of the first signal trace and to a second reference trace (314) of the second reference line on a second side of the first signal trace.

Abstract: System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space of a space of assignments for a set of generative variables. The method may further include applying the user defined distribution traits on the space of assignments for a set of generative variables to generate the random sub-space of the space of assignments for a set of generative variables. The method may also include testing a device under test using the generated random sub-space of the space of assignments for a set of generative variables.

Abstract: A method performed by an information handling system for on-the-fly technical support is described. In an exemplary method, an error message is read to obtain an error code therefrom. A project directory is searched to obtain a report; where the report indicates a failed module of a plurality of executable modules, and where the report is associated with the error message. A source of an error is identified from the error message. A failed stage of the failed module is identified from the report. A case inquiry for the error message is prepared for searching a document for resolution of the error, where the case inquiry identifies the failed stage. A network is accessed, and the case inquiry is sent over the network.

Abstract: When a wait statement is encountered in an HDL simulation, the simulation kernel executes functions corresponding to other processes while waiting for the wait to mature. However, the preservation of variables and states of each process and procedure in the call chain can be complex and inefficient. An embodiment of the present invention provides a method to suspend procedures in simulation of an HDL circuit design such that processes that call procedures containing wait statements are executed on a secondary runtime stack and can be suspended by saving the state of simulation and switching simulation execution to the primary runtime stack.

Abstract: A method is provided for communicating data between a first process and a second process. A set of inter-process functions of the first and second processes is determined. The set includes one or more functions of the first and second processes that are accessible by the other one of the first and second processes. An API definition file is generated. The API definition file includes a plurality of objects that each define a request to execute one or more inter-process functions of the set of inter-process functions. In response to input to the first process indicating a plurality of the inter-process functions, the plurality of inter-process functions are serialized according to the API definition file. The serialized set of functions is provided to the second process, using an FFI process, and deserialized according to the API definition file.