Abstract: Integrated circuit packaging devices and methods are disclosed. An embodiment package lid is formed from a single piece of material. The lid includes a planar rectangular main body having a bottom surface, and a leg disposed at each corner of the main body and within a perimeter of the main body. Each leg has a wall projecting downwardly from the main body and a non-planar bottom surface disposed at a bottom of the wall. The non-planar bottom surface of the leg faces a same direction as the main body bottom surface.

Abstract: Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.

Abstract: Approaches for testing a module of a circuit design include tagging flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language specification of the module. In simulating with the netlist, event data are captured to a first file. A process determines whether or not event data in the first file matches event data in a second file of event data. In response to a difference determined between the first file and the second file, an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file is determined. The one of the plurality of flip-flops that output the first signal is determined, and the respective path name of the one flip-flop is output.

Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Abstract: A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.

Abstract: A convolutional interleaver uses local memory of a first IC in combination with burst-type memory of a second IC. When a burst of data is read from memory of the second IC, one data value is provided to a data output and the remaining values are temporarily stored in local memory. After the memory of the second IC is initially filled, burst WRITE and burst READ operations provide efficient data transmission between the ICs.

Abstract: A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern.

Abstract: A circuit for enabling the transfer of data by an integrated circuit device is described. The circuit comprises a non-volatile memory array coupled to receive a clock signal and having a plurality of memory elements storing data; and a control circuit coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first mode and bi-directional transfer of data in a second mode; wherein the control circuit controls the transfer of data on the plurality of signal lines between the non-volatile memory array and the control circuit in the first mode on both the rising and falling edges of the clock signal. A method of enabling the transfer of data by an integrated circuit device is also described.

Abstract: Approaches for partially reconfiguring a frame are disclosed. In one approach, a circuit arrangement includes programmable resources, frames of configuration memory cells, and partial configuration control memory cells. Each frame includes a plurality of subsets of configuration memory cells, and each subset configures one of the programmable resources. Each partial configuration control memory cell is coupled to a respective one of the subsets. Responsive to a first partial bitstream that includes a quantity of configuration data for all the subsets of configuration cells of a first frame of the plurality of frames, each subset of the configuration memory cells of the first frame is configurable or not configurable responsive to the state of the associated partial configuration control memory cell.

Abstract: An integrated circuit for providing digital frequency synthesis is disclosed. For example, the integrated circuit comprises a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein the phase detector outputs an error signal. The integrated circuit further comprises a synthesizer control block, coupled to the phase detector, for receiving the error signal to generate a delay select signal, wherein the synthesizer control block comprises an integral adjustment filter and a proportional adjustment filter.

Abstract: A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described.

Abstract: A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.

Abstract: A packet processing circuit includes a plurality of header extraction circuits, and a scheduling circuit coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus having a plurality of data lanes. In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request, and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes.

Abstract: A network packet processor includes a plurality of processing pipelines and a scheduling circuit. Each processing pipeline is configured and arranged to process packets having sizes less than or equal to an associated processing size of the processing pipeline. The respective processing size of one of the processing pipelines is different from the processing size of at least one other of the processing pipelines. The scheduling circuit is coupled to the plurality of processing pipelines and is configured and arranged to determine respective packet sizes of packets input from a bus. The scheduling circuit assigns each packet of the one or more packets for processing by one of the processing pipelines as a function of the respective packet size of the packet and the processing size associated with the one of the processing pipelines.

Abstract: In an apparatus, an interconnect block includes a plurality of configuration memory cells. A plurality of multiplexers is respectively coupled to the configuration memory cells. An acknowledge circuit is coupled to the configuration memory cells. The acknowledge circuit includes a plurality of acknowledge inputs. The configuration memory cells are coupled to selectively set states of the plurality of multiplexers and correspondingly selectively activate inputs of the plurality of acknowledge inputs. A data ready circuit is coupled to at least one multiplexer output of the plurality of multiplexers.

Abstract: A method is provided for synthesizing an HLL program. For one or more variables to observe and/or control in a function of the HLL program, a first code segment is added to the function in the HLL program. For each of the one or more variables a respective second code segment is also added to the HLL program. In response to encountering the first code segment during synthesis of the HLL program, a memory is instantiated in a synthesized design. In response to encountering the second code segment during synthesis of the HLL program, a respective interface circuit is instantiated in the synthesized design. Each interface circuit is configured to replicate a state of the corresponding variable in the memory during operation of the synthesized design. A table is generated that maps names of the one or more variables to respective memory addresses in the memory.

Abstract: Approaches for Cholesky decomposition of a matrix are described. A first circuit is configured to generate an inverse square root of an input value. A second circuit is configured to generate a product of a value output by the first circuit and provided at a first input and a value provided at a second input. A third circuit is configured to generate a difference between a value provided at the first input and a value provided at the second input of the third circuit. The first input of the third circuit is coupled to the output of the second circuit. A control circuit is configured to iteratively distribute a plurality of values of the matrix and the outputs of the first, second, and third circuits to the inputs of the first, second, and third circuits such that the Cholesky decomposition of the matrix is output by the third circuit.

Abstract: An apparatus includes a first output stage and a first input stage of a first single track buffer, as well as a second output stage and a second input stage of a second single track buffer. The second single track buffer is downstream from the first single track buffer. The first output stage and the second input stage are coupled to one another via bidirectional rails. The first output stage and the second input stage in combination provide a first pulse generator.

Abstract: A communication system includes an iterative multi-stage decoder that may be dynamically configured to achieve a particular bit-error-rate. In one embodiment, a circuit comprises a first decoder block and a second decoder block to decode data received over a communication channel. A control circuit may change a number of iterations performed by the decoder blocks to decode received data based on a specified bit error rate and a detected signal-to-noise ratio of said received data. The number of computational units used in the decoders may be changed dynamically to achieve desired system performance. In one embodiment, resources are allocated based on a system initiating the connection. Programmable circuits are used in some embodiments to reconfigure the multi-stage decoder.

Abstract: Approaches are disclosed for testing a module of a circuit design. The module is simulated a first time using a testbench on a programmed processor. Event data is captured to a first file during the simulating. For each event, the event data describes a signal identifier, an associated signal value, and an associated timestamp. The event data of the first file is transformed into a hardware description language (HDL) replay module.