Abstract: Processing program code can include comparing functions specified in program code to identify a function group including a plurality of matching functions. A generalized function can be generated, using a processor, for the function group that implements an algorithm common to each of the plurality of matching functions. For each function of the function group, a wrapper function associated with the function can be generated, wherein each wrapper function calls the generalized function. A version of the program code including the generalized function and the wrapper function in place of each function of the function group can be created.

Abstract: A phase detection system can include a phase detector configured to determine a phase difference between a data stream and a first control signal and a numerically controlled oscillator configured to generate the first control signal responsive to a second control signal. The system can include a memory device having memory cells correlated with a cycle of the data stream. The memory device can be configured to increment the current memory cell according to a clock signal synchronized with the data stream. The system also can include an attenuator configured to attenuate the phase difference and generate an attenuated phase difference and an adder. The adder can be coupled to the memory device and be configured to generate a first sum of the attenuated phase difference and a value read from a current memory cell of the plurality of memory cells.

Abstract: An edge density detector is disclosed. This edge density detector is to receive a reference frequency signal and a feedback frequency signal. This edge density detector includes a first pulse generator, a second pulse generator, and a charge pump. The first pulse generator is coupled to receive the reference frequency signal and is configured to generate a first pulse signal. The second pulse generator is coupled to receive the feedback frequency signal and is configured to generate a second pulse signal. The charge pump is coupled to receive the first pulse signal and the second pulse signal to provide a control voltage signal. The control voltage signal is a phase independent with respect to the reference frequency signal and the feedback frequency signal.

Abstract: A method for detecting communications from multiple transmission antennas includes receiving a signal with at least one receive antenna, wherein the signal comprises data transmitted from at least one of the transmission antennas, calculating an equalized received signal and an equalized channel matrix using the signal and a channel matrix, determining whether a correlation factor threshold value is exceeded, and based on the act of determining, generating a listed based log likelihood ratio (LLR) soft output or a MMSE LLR soft output based on the equalized received signal and the equalized channel matrix.

Abstract: Within a system comprising a plurality of processors and a memory, a method of determining routing information for a circuit design for implementation within a programmable integrated circuit can include determining that nets of the circuit design comprise overlap and unrouting nets comprising overlap. A congestion picture can be determined that comprises costs of routing resources for the integrated circuit wherein the cost of a routing resource comprises a measure of historical congestion and a measure of current congestion, and wherein unrouted nets do not contribute to the measures of current congestion in the congestion picture. The method further can include concurrently routing a plurality of the unrouted nets via the plurality of processors executing in parallel according to the congestion picture and storing routing information for nets of the circuit design in the memory.

Abstract: In one embodiment, a network device is disclosed. For example, in one embodiment of the present invention, the device comprises a processor and a core memory having a receive buffer and a transmit buffer. The device comprises a bus coupled to the processor and the core memory. The device comprises at least one co-processor coupled to the core memory via a direct link, wherein the at least one co-processor is capable of accessing at least one of: the receive buffer, or the transmit buffer, without assistance from the processor.

Abstract: An embodiment of an integrated circuit is disclosed. This embodiment includes a processor programmed with a behavior model associated with power amplification. A calibration signal generator is coupled to the processor and configured to generate a digital calibration signal. The processor is coupled to receive a digital feedback signal. The processor is configured to determine at least one parameter associated with the power amplification in response to the digital feedback signal using the behavior model. The at least one parameter is selected from a group consisting of a nonlinearity order and a memory length. A digital predistorter is coupled for parameterization responsive to the at least one parameter.

Abstract: A computer-implemented method is described for determining cost in a non-blocking routing network that provides routing functionality using a single level of a plurality of multiplexers in each row of the routing network. The method includes assigning a respective numerical value, represented by bits, to each row of the routing network. A number of bits that differ between the respective numerical values of each pair of rows of the routing network indicates a number of row traversals necessary to traverse from a first row of the pair to a second row of the pair. A signal routing cost is computed from the number of bits that differ between the respective numerical values of the first row and the second row of the routing network. The calculated signal routing cost is provided to a placement module.

Abstract: Radix-based division is described. A dividend operand and a divisor operand are obtained. An estimate that is a reciprocal of the divisor operand is obtained. For a prescaling mode, a prescaling iteration is performed which includes: multiplying the divisor operand with the estimate to provide a prescaled divisor; apportioning the dividend operand into portions from most significant to least significant; providing the estimate to iteration blocks ordered from highest to lowest; providing the most significant to the least significant of the portions of the dividend operand respectively to the highest to the lowest of the iteration blocks; respectively multiplying the portions of the dividend operand with the estimate to provide first partial products; and parsing most significant residue portions and least significant residue portions as associated with order of the iteration blocks from the first partial products.

Abstract: In one embodiment, a block code decoder is provided. The block code decoder includes a first decoder configured to decode Bose-Chaudhuri-Hochquenghem (“BCH”) coded data packets and a second decoder configured to receive and decode Reed-Solomon (“RS”) encoded data from the first decoder. The first decoder includes a first buffer configured to receive BCH encoded data and one or more BCH decoder circuits coupled to the first buffer. Each BCH decoder circuit decodes a plurality of BCH encoded bits in parallel. A second buffer is arranged to store the decoded BCH data. The second decoder includes a third buffer, arranged to receive the RS encoded data from the first decoder, one or more RS decoder circuits configured to decode a plurality of RS encoded bits in parallel, and a fourth buffer arranged to store RS payload data decoded by the RS decoder circuits.

Abstract: The disclosure describes approaches for processing a circuit design. For each object of a plurality of objects of the circuit design, a respective key is generated as a function of a plurality of configuration parameter values of the object. Each object is renamed with a unique name that includes the key. A netlist of the circuit design is generated using the unique names and keys of the objects.

Abstract: A computer-implemented method of technology mapping a circuit design for implementation within a programmable logic device can include determining a plurality of cut sets for the circuit design, wherein each cut set includes a plurality of cuts. The method can include evaluating each cut set according to a cost function that depends, at least in part, upon a measure of inter-cut symmetry and selecting a cut set according to the cost function. Each cut of the selected cut set can represent an instantiation of at least one logic component within the programmable logic device. The circuit design specifying the selected cut set can be output.

Abstract: A bursty phase detector comprises upper and lower branches. The upper branch includes a voltage-controlled oscillator (VCO) providing a VCO phase; a phase detector with a first input for receiving a data stream and a second input coupled to the output of the VCO, the phase detector providing a phase error; a sample selector with a first input for receiving a sum of the VCO phase and the phase error, and a second input coupled to receive the data stream, the sample selector providing a data stream sample; a signal stream detector with a first input for receiving the sum of the VCO phase and the phase error, and a second input coupled to the output of the sample selector, the signal stream detector generating a data stream phase and a data stream detect signal. The lower branch includes a delay component with an input for receiving the data stream.

Abstract: A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist, mapping logic gates of the netlist to functionally equivalent standard cells, and including the standard cells within the standard cell circuit design. Design constraints for the standard cell circuit design can be automatically generated. The design constraints for the standard cell circuit design can be output.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: A circuit generates an output clock signal synchronized to an input clock signal. The circuit includes a reference clock port, a phase interpolator, and a phase controller. The reference clock port receives a reference clock signal. The phase interpolator generates the output clock signal that, as a function of a variable control value, is an interpolation between two reference phases. The reference phases are generated from the reference clock signal and have a reference frequency. The phase controller generates the variable control value providing a phase rotation rate. An output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate. The output frequency matches an input frequency of the input clock signal.

Abstract: One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.

Abstract: An embodiment of a decoder is disclosed. For this embodiment of the decoder, a first estimation unit and a second estimation unit are for iterative decoding. A scheduler is to receive a mode select signal to provide either an indication of first scheduling information or second scheduling information to the first estimation unit and the second estimation unit responsive to the mode select signal.

Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.