Abstract: A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.

Abstract: Approaches for selecting a field of data from a packet of data in an n-bit data path. A first selector circuit has m inputs and an output. The m inputs receive respective overlapping subsets of bits of the data path. The first selector selects one of the subsets of bits. Each stage of two or more shift-and-select stages includes a respective second selector circuit having up to m inputs. One of the inputs of the respective second selector circuit inputs an un-shifted version of the subset of bits, one or more others of the up to m inputs of the respective second selector circuit input different shifted versions of the subset of bits, and the respective second selector circuit outputs a selected one of the un-shifted or shifted versions of the subset of bits. The last shift-and-select stage outputs the field of data aligned to the least significant bit.

Abstract: Approaches for simulating a circuit design. A block diagram of the circuit design is displayed. Each block has at least one input and at least one output, and at least one of the input or output of each block is connected to another block. Simulation data are input to a simulation model of the circuit design. During simulation of each of a plurality of the sub-circuits with the simulation model, an output data value is determined from one or more input data values to the simulated sub-circuit. Concurrent with determining the output data value, an output tag value corresponding to the output data value is determined. Concurrent with output of the output data value from the simulated sub-circuit, each output tag value is displayed proximate an output signal line from the block corresponding to the sub-circuit.

Abstract: A method of performing a simulation of a design under test is disclosed. The method comprises implementing an input block having an adjustable output width; coupling test data to the input block; generating an input signal comprising the test data for the design under test according to an input requirement for the design under test by way of the input block; implementing an output block having an adjustable input width for receiving data from an output of the design under test; and coupling the output of the design under test to the output block according to an output requirement of the design under test. A circuit for enabling testing of a circuit design implemented in an integrated circuit is also disclosed.

Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

Abstract: Programmable logic devices (PLDs), programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), (collectively referred to as “PLDs”) can include circuitry for performing automatic erasing or “zeroization” of security information including data and programming. Such circuitry detects the occurrence of a possible security event, selects and/or forms one or more appropriate erase commands, and causes the command(s) to be executed against PLD memory. The circuitry prevents security information from being compromised under certain situations.

Abstract: A system for use within an integrated circuit (IC) can include an input differential pair including a positive input node and a negative input node, a current source coupled to the input differential pair, and a current mirror. The current mirror can include at least a first active device and a second active device. The system can include a biasing transistor device having a source terminal coupled to a gate terminal of each of the first and second active devices, a gate terminal coupled to a drain terminal of the second active device, and a drain terminal coupled to a voltage source. The biasing transistor device is complementary to the current mirror.

Abstract: A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.

Abstract: One embodiment of an integrated circuit includes a local circuit block, a first power supply for supplying power to a first terminal of the local circuit block, a second power supply for supplying power to a second terminal of the local circuit block, a first transmission gate coupled between the second terminal of the local circuit block and a current path from the second power supply, and a second transmission gate coupled between the current path from the second power supply and a gate of a p-type metal-oxide-semiconductor (PMOS) transistor in the first transmission gate, the second transmission gate including a single transistor.

Abstract: An embodiment of an interposer is disclosed. For this embodiment of the interposer, a first circuit portion is created responsive to a first printing region. A second circuit portion is created responsive to a second printing region. The interposer has at least one of: (a) a length dimension greater than a maximum reticle length dimension, and (b) a width dimension greater than a maximum reticle width dimension.

Abstract: A method is provided for exporting design constraints from a circuit design. In response to a first user command indicating a design constraint and a pattern, the design constraint is assigned to each object in the circuit design that matches the pattern, and the pattern is stored in a database. In response to a second user command to export design constraints of the circuit design, for each design constraint assigned to a respective set of objects of the circuit design, a pattern stored in the database that matches the respective set of the objects is determined and the design constraint is added to an export file in a format that uses the determined pattern. Design constraints on individual ones of the set of the objects indicated by the determined pattern are omitted from the export file.

Abstract: A memory write interface in an integrated circuit (IC) and method of providing the same are described. An aspect relates to an apparatus for providing an input/output (IO) interface in a programmable device. The apparatus can include: a memory write interface configured to drive a memory having a daisy-chained clock, a first interface configured to receive output data from the programmable device and a second interface configured to control transmission of the output data to the memory by an IO element of the programmable device, the first interface operating according to a global clock of the programmable device and the second interface operating according to a local clock used only by the IO interface; a delay circuit configured to add a delay to the local clock with respect to the global clock; and a configuration circuit configured to adjust the delay added to the local clock to implement write-leveling at the memory.

Abstract: A memory arrangement includes a plurality of memory blocks, a first group of access ports, and a second group of access ports. Routing circuitry couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block, and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion, and has read access to the first portion but not to the second portion.

Abstract: An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

Abstract: In one embodiment, a method for implementing quality of service (QOS) processing in a data bus interface. Each input read/write command is stored in a first-in-first-out queue. Each input read/write command includes a respective QOS value. In response to an input first read/write command having a QOS value higher than the QOS value of the read/write command at a head of the first-in-first-out queue, the QOS value of each of a first number of read/write commands is increased as each read/write command is removed from the head of the first-in-first-out queue.

Abstract: A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.

Abstract: A method and apparatus for providing a program-based hardware co-simulation of a circuit design are described. In one example, a circuit design is implemented for programmable logic to establish a design under test (DUT). A co-simulation model is programmatically generated using primitives defined by an application programming interface (API). The circuit design is simulated by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the co-simulation model.

Abstract: A method of loading configuration data within an integrated circuit that includes multiple dies is disclosed. The method can include receiving configuration data in encrypted form within a first die of the multiple dies of the integrated circuit and decrypting the configuration data within the first die to generate configuration data in unencrypted form. A portion of the configuration data in unencrypted form can be distributed from the first die to each other die of the multiple dies through an interposer to which each die is attached.

Abstract: A method of debugging an integrated circuit (IC) can include receiving, within a debugging system implemented within the IC, a debug command from a system external to the IC and, responsive to the debug command, initiating a debug function specified by the debug command for a processor system embedded on the IC. An IC also is provided that can include a programmable circuitry (e.g., a programmable fabric) coupled via an interface to processor system embedded in the IC. A debugging system can be implemented within the programmable fabric to communicate with the processor system via the interface.

Abstract: An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.