Abstract: A method of debugging within an integrated circuit (IC) that includes an embedded processor can include detecting an event within a circuit of the IC that is external to the processor and, responsive to detecting the event, initiating a debug function within the processor. Similarly, responsive to detecting an event within the processor, a debug function within a circuit block of the IC that is external to the processor can be initiated. Trace data generated within the processor and trace data generated within the programmable fabric further can be merged to generate combined trace data.

Abstract: Automatic queue sizing for data flow applications for an integrated circuit is described. Queue sizes for queues of a dataflow network are initialized to a set of first sizes for running as distributed actors without having to have centralized control. If it is determined there is a deadlock, causes for the dataflow network being deadlocked are analyzed with a controller coupled thereto to select a first actor thereof. The first actor of the dataflow network is selected as being in a stalled write phase state. Queue size is incremented for at least one queue of the queues to unlock the first actor from the stalled write phase state. The running, the determining, the analyzing, and the incrementing are iteratively repeated to provide a second set of sizes for the queue sizes sufficient to reduce likelihood of deadlock of the data flow network.

Abstract: Alignment of a clock signal to a particular phase is described. In one aspect, a method includes receiving an incoming clock signal and multiple phased clock signals, each of the phased clock signals having a different phase and a substantially same phase offset from another phased clock signal. At least one detection signal based on the incoming and phased clock signals is provided, and one or more errors contributed by noise in at least the incoming clock signal are corrected in the at least one detection signal. Based on the at least one detection signal, one of the phased clock signals is selected as the most closely aligned of the phased clock signals to the predetermined clock phase, and the selected clock signal is output.

Abstract: A method is provided for generation of a circuit design. A set of design assistance rules is retrieved from a database. Each design assistance rule in the set includes a list of design objects to which the design assistance rule applies, a set of criteria to be satisfied by the circuit design before the design assistance rule may be applied, a set of configuration options, and an executable script configured to perform an automated configuration of the circuit design. In response to a change in the circuit design, applicable design assistance rules are determined based on the corresponding sets of criteria. In response to determining that one or more design assistance rules are applicable, data indicating that the one or more design assistance rules are available is output. In response to input that selects a design assistance rule the executable script corresponding to the selected design assistance rule is executed.

Abstract: Digital signal processing and, more particularly, digital video coding is described. Video encoding or decoding of frames includes accessing a plurality of values that can include at least one quantized DC default value and a plurality of quantized DC block values for neighboring blocks with respect to an intra block. A direction of change for the intra block is determined using predictor values obtained from the accessed values.

Abstract: A FIR filter component for a voltage mode driver includes a first node, a second node, and a first switching component comprising a first transistor having a first drain/source, a gate, and a second drain/source, and also a second transistor having a first drain/source, a gate, and a second drain/source. The FIR filter component also includes a first tunable resistor coupled between the first node and a first potential, and a second tunable resistor coupled between the second node and a second potential, wherein the FIR filter component is configured to generate a first output signal at the first output node.

Abstract: Methods and systems redundantly validate values that are stored in a memory arrangement. The memory arrangement includes a first port and a second port that provide coherent access to one or more caches in the memory arrangement, and the first and second ports provide this coherent access at the same priority level. An instruction processor verifies that a first expected value matches a first check value calculated from the values as read from the memory arrangement via the first port. A check circuit verifies that a second expected value matches a second check value calculated from the values as read from the memory arrangement via the second port. A recovery operation is performed in response to the first or second expected values not matching the first and second check values, respectively.

Abstract: An integrated circuit having secure configuration includes configuration memory, programmable logic resources coupled to the configuration memory, programmable interconnection resources coupled to the configuration memory and programmable logic resources, and a configuration controller circuit coupled to the configuration memory. The configuration controller circuit is configured to read values from a configuration memory address of a portion of the configuration memory in response to a configuration memory address contained in input configuration data, and to decrypt the input configuration data using the values as a decryption key. The configuration controller is further configured to program the configuration memory of the integrated circuit with the decrypted input configuration data.

Abstract: An embodiment of a technique to capture and locally synchronize data is disclosed. The technique includes receiving first and second signals through a first interface, and receiving a third signal through a second interface where the third signal is unsynchronized with respect to the second signal. The technique further includes detecting a first phase difference between the second and third signals, and generating a fourth signal in a manner so that a second phase difference between the fourth signal and one of the second or third signals is a function of the first phase difference. In addition, the technique includes storing a state of the first signal in response to the fourth signal, and thereafter supplying the stored state of the first signal to the second interface.

Abstract: In one embodiment, a circuit arrangement for performing cryptographic operations is provided. The circuit includes a substitution block, a cryptographic circuit coupled to the substitution block, and a balancing circuit coupled to the substitution block. The substitution block includes a memory unit storing substitution values and ones-complement values that are corresponding ones-complements of the substitution values. The substitution block, responsive to a request to read a specified one of the substitution values, concurrently reads and outputs the specified substitution value and the corresponding ones-complement value. A power consumed in reading the specified substitution value is uniform with a power consumed in reading another one of the substitution values. The cryptographic circuit and the balancing circuit are configured to concurrently operate on each substitution value and the corresponding ones-complement value read from the memory, respectively.

Abstract: A method of providing non-volatile memory in an integrated circuit is disclosed. The method may comprise storing a plurality of data blocks in volatile memory elements of the integrated circuit, wherein each data block of the plurality of data blocks comprises a plurality of data bits; reading back the plurality of data bits associated with a data block of the plurality of data blocks; determining, by a control circuit, whether values read back for the plurality of data bits associated with the data block indicate valid data in the data block; and reading back, for another data block of the plurality of data blocks, stored data bits to determine a value for the other data block. A circuit for providing non-volatile memory in an integrated circuit is also disclosed.

Abstract: In one embodiment, a method and apparatus for analyzing a design of an integrated circuit (IC) are disclosed. For example, the method parses a netlist file of the IC where a module of the IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure. The method traces through a connectivity of the plurality of sub-modules, and tabulates data associated with the connectivity with a fault cost associated with a structure of the IC.

Abstract: A configurable multiplier circuit for multiplying both real and complex numbers is included in a PLD. In one embodiment, the circuit includes two adder trees. Multiplexers are used such that a conventional multiplier component is not required. The circuit is programmable to operate in one of two modes. In a first mode, the circuit multiplies the four parts of two complex numbers and outputs two values, the real portion of the product and the imaginary portion of the product. In a second mode, each of two portions of the circuit multiplies two pairs of real numbers and outputs the products.

Abstract: In one embodiment, a concurrent processing system is disclosed. For example, in one embodiment of the present invention, a concurrent processing system, comprises a first processing element comprising a first monitor module, a second processing element in communication with the first processing element, the second processing element comprising a second monitor module, and a first system monitor for receiving a notification from at least one of: the first processing element, or the second processing element, wherein the notification indicates an event detected by one of the first monitor module, or the second monitor module.

Abstract: Parameterization of a CORDIC algorithm for providing a CORDIC engine is described. An aspect of the invention is a method in a digital processing system for generation of the CORDIC engine. Numbers of fractional output bits for a user-defined numerical result format are obtained. The numbers of fractional output bits are for each of a plurality of output variables associated with the CORDIC algorithm. Micro-rotations associated with each of the plurality of output variables are determined responsive to the numbers of fractional output bits. Quantizations associated with each of the plurality of output variables are determined responsive at least in part to the numbers of fractional output bits.

Abstract: A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.

Abstract: An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer.

Abstract: In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency sub-clocks for a destination in the VLSI system, distributing each lower-frequency sub-clock of the one or more pairs of lower-frequency sub-clocks to a corresponding channel coupled to the destination, and reconstructing a reference master clock signal at the destination from the one or more pairs of lower-frequency sub-clocks, wherein the reconstructed reference master clock signal replicates the original master clock signal.

Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

Abstract: A method for automating input/output buffer information specification (IBIS) model generation. A wrapper utility combines components into an automated generation flow to model multiple input/output (I/O) buffers that conform to single-ended and differential I/O standards. Configuration data files are imported to properly configure the modeled I/O buffers according to a specific set of signal parameters across all process corners. Output and input termination impedance may also be modeled within the I/O buffer. A simulation setup file of the modeled I/O buffer is generated to determine the voltage/current (V/I) and voltage/time (V/T) data for the modeled I/O buffer for each process corner. A raw IBIS model is then created, formatted, and validated to determine the accuracy of the IBIS model. Execution steps of the IBIS model generator are then iterated to automatically generate, correlate, and compile IBIS models for each I/O standard into a single file.