Patents Assigned to Xilinx, Inc.
  • Method and system for preparing modularized circuit designs for dynamic partial reconfiguration of programmable logic
    Patent number: 8560996
    Abstract: Approaches for dynamically reconfiguring a programmable integrated circuit (IC) are disclosed. In response to user input to a reconfiguration controller while a circuit is operating in programmable resources of the programmable IC, a replacement module and a module to be replaced in the circuit are selected. A process determines whether or not interfaces of the replacement module are compatible with interfaces of the circuit to the module to be replaced. In response to the interfaces of the replacement module and the interfaces of the circuit to the module to be replaced being compatible, the programmable IC is partially reconfigured with a realization of the replacement module in place of a realization of the module to be replaced.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 15, 2013
    Assignee: Xilinx, Inc.
    Inventors: Gordon J. Brebner, Christopher E. Neely
  • Suspension of procedures in simulation of an HDL specification
    Patent number: 8560295
    Abstract: In one embodiment, a method to simulate an HDL specification is provided. For each call to a procedure, an intermediate process is dynamically created during simulation. The process containing the call to the procedure is replaced with the intermediate process in an active process list of processes scheduled for execution. The intermediate process is configured to call the procedure and, in response to completing execution of the procedure, cause the simulator to add the calling process to the front of the active process list and remove the intermediate process from the active process list.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 15, 2013
    Assignee: Xilinx, Inc.
    Inventors: Sonal Santan, Pratima Gupta
  • Serializer/deserializer frontend
    Patent number: 8559145
    Abstract: A receiver frontend includes a first input junction for receiving a first input signal, a second input junction for receiving a second input signal, a first output junction, a second output junction, and circuitry configured to perform equalization on the first input signal and the second input signal to establish a first output signal with a desired frequency response at the first output junction, and to establish a second output signal with a desired frequency response at the second output junction, and perform common-mode voltage adjustment on a common-mode voltage associated with the first output signal and the second output signal.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Xilinx, Inc.
    Inventors: Vassili Kireev, Jafar Savoj
  • Integrated circuit design using through silicon vias
    Patent number: 8560982
    Abstract: A method of integrated circuit design using through silicon vias (TSVs) can include determining that a stress field to which a first active circuit element of a circuit block is exposed and a stress field to which a second active circuit element of the circuit block is exposed are mismatched. Mismatch between the stress field of the first active circuit element and the stress field of the second active circuit element can be reduced by modifying a layout of the die for a TSV.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 15, 2013
    Assignee: Xilinx, Inc.
    Inventor: Arifur Rahman
  • System and method for pilot tone assisted selected mapping
    Patent number: 8553786
    Abstract: A method is provided for communicating a data value and pilot tone within the same communication sub-carrier of a communication channel. A first reference phase corresponding to a first data value is selected. A pilot tone having the first reference phase is generated. The generated pilot tone is transmitted. The transmitted pilot tone is received. A phase of the received pilot tone is determined. A second data value is determined from the phase of the received pilot tone. The second data value is stored in an electronic storage medium.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: October 8, 2013
    Assignee: Xilinx, Inc.
    Inventor: Christopher H. Dick
  • Classifying a criticality of a soft error and mitigating the soft error based on the criticality
    Patent number: 8549379
    Abstract: Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: October 1, 2013
    Assignee: Xilinx, Inc.
    Inventors: Alfred L. Rodriguez, Nicholas J. Possley, Kevin Boshears, Austin H. Lesea, Jameel Hussein
  • Disposing underfill in an integrated circuit structure
    Patent number: 8546191
    Abstract: In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: October 1, 2013
    Assignee: Xilinx, Inc.
    Inventor: Arifur Rahman
  • System and method for automated configuration of design constraints
    Patent number: 8549454
    Abstract: In one embodiment, a method for propagating design constraints between a module and a module instance in a circuit design is provided. A port of the module and a port/pin of the circuit design are determined, between which constraints are to be propagated. The determination of the port/pin includes determining whether or not pin of the module instance corresponding to the port is directly connected to a top-level port of the circuit design. In response to determining that the pin is directly connected to a top-level port, the top-level port is selected as the port/pin. In response to determining that the pin is not directly connected to the top-level port, the pin is selected as the port/pin. Design constraints are propagated between the port and the selected port/pin. The propagated design constraints are stored in a storage device.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: October 1, 2013
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, David A. Knol, Frederic Revenu, Dinesh K. Monga
  • Signal level control
    Patent number: 8549057
    Abstract: An embodiment of a method for control of signal level is disclosed. In such an embodiment, a number for a pre-cursor set, a number for a cursor set, and a number for a post-cursor set are set corresponding to a weighted contribution of a pre-cursor symbol, a weighted contribution of a cursor symbol, and a weighted contribution of a post-cursor symbol, respectively, for the signal level. A number associated with a high-impedance set is determined. The number associated with the high-impedance set is determined by subtracting the number for the pre-cursor set, the number for the cursor set, and the number for the post-cursor set from a total available amount of units. The high-impedance set provides no weighted contribution to the signal level. Data is transmitted using the signal level set responsive to the pre-cursor set, the cursor set, and the post-cursor set.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 1, 2013
    Assignee: Xilinx, Inc.
    Inventors: Cheng Hsiang Hsieh, Paul-Hugo Lamarche, Arif Akram Siddiqi
  • Multi-die stack package
    Patent number: 8546955
    Abstract: An embodiment of an apparatus is disclosed. This embodiment of the apparatus includes an interposer, a first die stack, a second die stack, a third die stack, and a fourth die stack which are all coupled to the interposer. The interposer provides a common base for and a stratum of each of the first die stack, the second die stack, the third die stack, and the fourth die stack. The first die stack includes an optical engine. The optical engine includes at least one optical engine die. The second die stack includes a plurality of programmable resource dies. The third die stack includes at least one memory die. The fourth die stack includes a serializer-deserializer die.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: October 1, 2013
    Assignee: Xilinx, Inc.
    Inventor: Ephrem C. Wu
  • Integrated circuit enabling the communication of data and a method of communicating data in an integrated circuit
    Patent number: 8548071
    Abstract: An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 1, 2013
    Assignee: Xilinx, Inc.
    Inventor: Anthony J. Collins
  • PARALLEL ENCODING FOR NON-BINARY LINEAR BLOCK CODE
    Publication number: 20130254639
    Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 26, 2013
    Applicant: XILINX, INC.
    Inventors: Kalyana Krishnan, Hai-Jo Tarn
  • Digital signal processing block with preadder stage
    Patent number: 8543635
    Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: September 24, 2013
    Assignee: Xilinx, Inc.
    Inventors: James M. Simkins, Alvin Y. Ching, John M. Thendean, Vasisht M. Vadi, Chi Fung Poon, Muhammad Asim Rab
  • Methods and apparatus for testing of integrated circuits
    Patent number: 8542029
    Abstract: Methods and apparatus for testing packaged ICs are disclosed. In some embodiments, an apparatus for testing a packaged integrated circuit (IC) can include a pre-test station having a height detection system configured to detect a height of a packaged IC when disposed therein prior to testing; a testing station for testing the packaged IC received from the pre-test station; and a device handler for moving the packaged IC to the testing station. In some embodiments, a method for testing packaged ICs may include detecting a height of a packaged IC to be tested disposed in a pre-test station; comparing the height to an expected height; and determining whether the detected height of the packaged IC is different than the expected height of the packaged IC by greater than or equal to a desired amount.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: September 24, 2013
    Assignee: Xilinx, Inc.
    Inventor: Mohsen Hossein Mardi
  • Method and integrated circuit for protecting against differential power analysis attacks
    Patent number: 8539254
    Abstract: In one embodiment of the invention, a method is provided for protecting against attacks on security of a programmable integrated circuit (IC). At least a portion of an encrypted bitstream input to the programmable IC is decrypted with a cryptographic key stored in the programmable IC. A number of failures to decrypt the encrypted bitstream is tracked. The tracked number is stored in a memory of the programmable IC that retains the number across on-off power cycles of the programmable IC. In response to the number of failures exceeding a threshold, data that prevents the decryption key from being used for a subsequent decryption of a bitstream is stored in the programmable IC.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 17, 2013
    Assignee: Xilinx, Inc.
    Inventors: Brendan K. Bridgford, Jason J. Moore, Stephen M. Trimberger, Eric E. Edwards
  • Output driver and method of operating the same
    Patent number: 8536894
    Abstract: In an integrated circuit for an output interface, a comparator is used to compare a reference voltage and a regulated voltage to provide a comparison output. A state machine is coupled to the comparator to increment or decrement a resistance setting output of the state machine responsive to the comparison output. A reference single-ended driver is coupled to receive the resistance setting output from the state machine. An output node of the reference single-ended driver is coupled to a reference node. From the reference node, the reference voltage is input to the comparator as a feedback voltage. Transistors of the reference single-ended driver are set to be in either at least a substantially conductive state or at least a substantially non-conductive state responsive to the resistance setting output to provide an internal source termination resistance as a reference resistance.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: September 17, 2013
    Assignee: Xilinx, Inc.
    Inventor: Sing-Keng Tan
  • Method and apparatus for self-annealing multi-die interconnect redundancy control
    Patent number: 8539420
    Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: September 17, 2013
    Assignee: Xilinx, Inc.
    Inventor: Rafael C. Camarota
  • Programmable interconnect element and method of implementing a programmable interconnect element
    Patent number: 8536896
    Abstract: A programmable interconnect element for an integrated circuit device is described. The programmable interconnect comprises a first selection circuit coupled to a plurality of input lines and having a first output; a register having a first input coupled to the first output; and a second selection circuit enabling the selection of a value at the first output or a value stored by the register. A method of implementing a programmable interconnect element is also disclosed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: September 17, 2013
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Method and implementation of cyclic redundancy check for wide databus
    Patent number: 8539326
    Abstract: A method for computing a X-bit cyclical redundancy check (CRC-X) frame value for a data frame transmitted over a N-bit databus is provided. The method includes receiving a N-bit data input with an end-of-frame for the data frame at bit position M on the N-bit databus, performing a bitwise XOR on X most significant bits of the N-bit data input with a CRC-X feedback value to form a first N-bit intermediate data. The method also includes shifting the first N-bit intermediate data by M bit positions to align the end-of-frame of the data frame with a least significant bit (LSB), and padding M number of zero bits to a most significant bit (MSB) of the first N-bit intermediate data to form a second N-bit intermediate data.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 17, 2013
    Assignee: Xilinx, Inc.
    Inventors: Mark R. Nethercot, Martin B. Rhodes, Gareth D. Edwards
  • Uniform power regulation for integrated circuits
    Patent number: 8536935
    Abstract: A system for uniform power regulation of an integrated circuit is disclosed. In each of a plurality of regions, the system includes a comparison circuit having a first input coupled to receive a reference voltage and a second input coupled to receive a feedback voltage. The comparison circuit provides a gating voltage to a driver circuit that is coupled to a first supply voltage. The driver circuit is configured to provide a regulated voltage responsive to the gating voltage. A feedback adjustment circuit is configured to trim the regulated voltage by a region-specific trim value and output the trimmed regulated voltage as the feedback voltage on the output.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: September 17, 2013
    Assignee: Xilinx, Inc.
    Inventors: Thomas P. LeBoeuf, Eric E. Edwards