Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed.

Abstract: A device having programmable logic for implementing arithmetic functions is disclosed. The device comprises an input port coupled to receive a configuration bitstream; a plurality of configurable arithmetic blocks, each configurable arithmetic block comprising configurable circuits for implementing arithmetic functions according to bits of the configuration bitstream; a plurality of input registers coupled to receive multi-bit input words to be processed by the plurality of configurable arithmetic blocks; and an output register enabled to generate an output word. A method of implementing an arithmetic function in a device having programmable logic is also disclosed.

Abstract: A method is provided for testing a circuit design in a programmable IC. The circuit design and a sampling circuit are implemented in the programmable IC. A first routing circuit is implemented in the programmable IC to route signals from the designated locations of a first subset of a set of test nodes of the circuit design to a set of input nodes of the sampling circuit. Signals are sampled from the first subset of test nodes using the sampling circuit. The programmable IC is partially reconfigured to implement a second routing circuit that replaces the first routing circuit. The second routing circuit is configured to route signals from a second subset of the set of test nodes to the set of input nodes of the sampling circuit. Signals from the second subset of test nodes are sampled using the sampling circuit.

Abstract: In a multiplier architecture, all stages of a multiplication function are implemented using a uniform array of logic blocks. An exemplary multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each logic block includes a multiply block and a logic circuit driven by the multiply block. The logic circuit is coupled to implement an add function. A first portion of the array is coupled to receive the first and second multiplicand inputs, to provide a partial product bus, and to provide lower bits of the product output. A second portion is coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output. The multiply blocks may be non-uniform arrays, e.g., logical AND gates and full adders in all but one column, with only logical AND gates in the remaining column.

Abstract: In one embodiment of the present invention a secure cryptographic device is provided. The device includes a power supply interface, a cryptographic processing block coupled to the power supply interface, a random number generator, and a complex multiplication circuit. The complex multiplication circuit has an output coupled to the power supply interface for modulating a power variation waveform detectable on the power supply interface. The complex multiplication circuit also has a first input coupled to an output of the random number generator and a second input coupled to the power supply interface.

Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.

Abstract: Method and apparatus for electrically charactering an integrated circuit (IC) are described. In an example, a data line in conductive interconnect of the IC is identified that is failing. First and second vertical trenches are milled in the IC along the data line to expose respective first and second cross-sections of the conductive interconnect having the data line. First and second probes are placed in contact with the data line in the first and second vertical trenches, respectively. A determination is made whether the data line is open or shorted between the first and second vertical trenches using an electrical measurement device coupled to the first and second probes.

Abstract: In one embodiment, a method of detecting corruption of configuration memory is provided. A bitstream of a circuit design that includes at least a first module and a second module is generated. Configuration memory cells used to implement each of the first and second modules are determined. The configuration memory cells are programmed with the bitstream. After programming, configuration memory cells used to implement the first module are checked for corruption at a first frequency, and configuration memory cells used to implement the second module are checked for corruption at a second frequency, with the first frequency being different from the second frequency.

Abstract: A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract: Approaches for analyzing a power grid of an integrated circuit are described. In one embodiment, a method includes selecting at least one portion of the integrated circuit to be analyzed. A power grid model corresponding to the integrated circuit is retrieved from a database, and a first simulation of the programmable integrated circuit is performed. The first simulation generates a respective waveform of an electrical characteristic over time for each connection of a component within the selected portion to voltage supply or voltage ground. A simulation is performed of the power grid model using the respective waveforms as input stimulus for each connection in the selected portion.

Abstract: The semiconductor device includes a semiconductor substrate of a first type. A layer of semiconductor material of a second type is disposed on the semiconductor substrate. A first well and a second well are disposed on the layer. A third well is disposed on the layer between the first and second wells. A memory cell, including a first and a second plurality of transistors of the second type and a third plurality of transistors of the first type, is formed in the first, second, and third wells. The first plurality of transistors is formed in the first well, the second plurality of transistors is formed in the second well, and the third plurality of transistors is formed in the third well. The layer and the third well are configured to isolate the first and second wells from each other and from the semiconductor substrate.

Abstract: In one embodiment, an interposer resistant to warping is provided. The interposer includes a semiconductor body having a first contact array included on a first side of the semiconductor body. Vias are formed through the semiconductor body. One or more wiring layers are included on the first side of the semiconductor body. The wiring layers electrically couple each contact of the first contact array to a respective one of the vias. Contacts of a second contact array, included on a second side of the semiconductor body, are respectively coupled to the vias. A stabilization layer is included on the second side of the semiconductor body. The stabilization layer is configured to counteract stresses exerted on a front side of the interposer due to thermal expansion of wiring layers.

Abstract: Methods and apparatus for receiving high voltage signals using a receiver designed in a low supply voltage technology are disclosed. One embodiment of an integrated circuit includes a single ended driver including an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor. An input pass gate is coupled to the single ended driver, and is configured as a PMOS pass gate coupled in parallel with the NMOS transistor in the single ended driver. In a low voltage mode, the NMOS transistor and the PMOS pass gate form a first pass gate for transmitting the input signal to the receiver. In a high voltage mode, the PMOS pass gate is disabled, and the NMOS transistor and PMOS transistor form a second pass gate for transmitting the input signal to the receiver.

Abstract: Decoupling capacitor circuit assembly is described. In one example, a circuit assembly includes a passive substrate, a plurality of terminals, and at least one capacitor. The passive substrate includes a top surface and a bottom surface. The plurality of terminals is formed on the top surface and is configured for electrical communication with a respective plurality of lands on a printed circuit board (PCB). The at least one capacitor is mounted to the bottom surface of the passive substrate and is configured to provide decoupling capacitance for an integrated circuit (IC) on the PCB. Each capacitor is coupled to a pair of the plurality of terminals. In another example, a circuit assembly includes a PCB, and IC mounted to the PCB, a passive substrate mounted to the PCB, and at least one capacitor mounted to the passive substrate for providing decoupling capacitance for the IC.

Abstract: Approaches for operating a programmable integrated circuit (IC) are disclosed. One configuration bitstream of two or more configuration bitstreams is selected. Each configuration bitstream implements a functionally equivalent circuit on the programmable IC and programs a respective subset of pass gates of the programmable IC. Each subset of pass gates programmed by the configuration bitstreams is disjoint from each other subset of pass gates. The programmable IC, which is defect-free, is configured with the selected configuration bitstream. The defect-free programmable IC is then operated for a period of time. The selecting, configuring and operating are repeated, and for successive selecting operations, different ones of the configuration bitstreams are selected.

Abstract: Approaches for placement and routing of a circuit design are disclosed. Two or more modules of a circuit design are assigned to respective regions of a programmable integrated circuit. Placement and routing constraints are created for non-global resources of two or more modules of the circuit design. The placement and routing constraints restrict placement and routing of non-global resources of each of the two or more modules to respective regions of a programmable IC. Each non-global resource is used by at most one of the two or more modules. The two or more modules are placed. In response to the one of the placed circuit elements not being placed within the assigned region, the routing constraint on the one of the circuit elements is removed. The circuit design is routed.

Abstract: In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second source/drain is coupled to the third node. The RC-triggered clamp also has an inverter, wherein an input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor. The ESD protection circuit also includes one or more forward-biased diodes coupled in series between a supply node and the first node.

Abstract: Embodiments of stacked die assemblies for an IC are disclosed. One embodiment includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer.

Abstract: One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.