Abstract: A system can include write circuitry configured to implement a write finite state machine selected from a plurality of write finite state machines and read circuitry configured to implement a read finite state machine selected from a plurality of read finite state machines. The system also can include a multi-port memory having a write port controlled by the write circuitry and a read port controlled by the read circuitry. The write circuitry and the read circuitry can be configured to implement the selected write finite state machine and the selected read finite state machine to perform one of a plurality of different data transformations using the multi-port memory.

Abstract: A method of correcting adjacent bit errors in a memory is disclosed. The method comprises determining that there are errors in each set of two non-overlapping sets of the memory; changing a stored value of a memory cell of the memory until it is determined that a single error exists in the memory; identifying a location of the single error in the memory; and correcting the single error in the memory. A circuit for detecting adjacent bit errors in a memory having alternating even memory cells and odd memory cells is also disclosed.

Abstract: Methods for matrix processing and devices therefor are described. A systolic array in an integrated circuit is coupled to receive a first matrix as input; and is capable of operating in two modes, namely a triangularization mode and a back-substitution mode. The systolic array, when in a triangularization mode, is coupled to triangularize the first matrix to provide a second matrix. When in a back-substitution mode, the systolic array is coupled to invert the second matrix.

Abstract: An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.

Abstract: In one embodiment, a method is provided for analyzing a circuit design. For each sub-circuit of a plurality of sub-circuits specified in the circuit design, a logic level probability is determined for each output of the sub-circuit. The logic level probability indicates the probability that an output of the sub-circuit will have a first value in response to possible values of inputs to the sub-circuit. Each logic level probability is converted to a switching probability that indicates a probability that a switching event will occur at the respective output of the sub-circuit within a time period. The switching probability is stored in a memory.

Abstract: A method of determining a shift pattern for generating an output data stream comprising output data words having a data width N from input data words having a data width M is disclosed. The method comprises receiving an input data stream comprising words having the data width M; determining a ratio based upon the data width N and the data width M; determining an initial shift value; generating subsequent shift values of the shift pattern based upon the initial shift value and the ratio based upon the data width N and the data width M, and transforming the input data stream to the output data stream by shifting input data words of the input data stream according to the shift pattern using a barrel shifter or a multiplexer network. A circuit for generating an output data stream comprising output data words having a width N from input data words having a width M is also disclosed.

Abstract: Approaches for crest factor reduction in a multiband transmitter. An input data signal is placed on a first frequency band, and a second frequency band that is inactive is selected. The second frequency band is out-of-band from the first frequency band. A peak-reducing waveform placed on the second frequency band is generated. The peak-reducing waveform is configured to reduce a plurality of peaks in the data signal. The peak-reducing waveform and the data signal are combined to produce a crest-factor-reduced signal. The crest-factor-reduced signal is transmitted from the multiband transmitter.

Abstract: According to an embodiment, a method of preventing the alteration of a stored data value is disclosed. The method comprises coupling a first electronic fuse to an output control circuit; coupling a second electronic fuse to the output control circuit; decoding the states of the first electronic fuse and the second electronic fuse after a first processing step to generate a first decoded state; and decoding the states of the first electronic fuse and the second electronic fuse after a second processing step to generate a second decoded state different from the first decoded state; wherein the output control circuit maintains the second decoded state after an attempt to alter a state of an electronic fuse of the first electronic fuse and the second electronic fuse. A circuit for preventing the alteration of a stored data value is also described.

Abstract: A memory structure can include a first memory block including a plurality of memory cells corresponding to a first subset of addresses of a range of addresses and a second memory block including a plurality of memory cells corresponding to a second subset of addresses of the range of addresses. The memory structure can include control circuitry coupled to the first memory block and the second memory block and configured to provide control signals to the first memory block and the second memory block. The first memory block and the second memory block can be configured to implement a reduced power mode independently of one another responsive to the control signals.

Abstract: A multiplexer-based network provides the routing equivalent to a non-blocking crossbar network having a plurality of crossbar switches making up an ingress, middle, and egress stages. The non-blocking crossbar network includes crossbar rows, each including outbound and inbound internal connections to another crossbar row. The multiplexer-based network includes multiplexer-based network rows. Each multiplexer-based network row corresponds to a crossbar row of the crossbar network and includes at least one global input, at least one global output, internal inputs, internal outputs, and a corresponding set of multiplexers. Each set of multiplexers includes an internal multiplexer for each respective outbound internal connection of the respective crossbar row. The internal multiplexer includes inputs for signals routable to the respective outbound internal connection. At least one global multiplexer provides a signal to a global output of the multiplexer-based network row.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.

Abstract: A shorted test structure and methods for making it are disclosed. A conductive layer is applied over a first surface of a blank substrate. The blank substrate has a plurality of conductive vias that electrically connect solder lands on the first surface of the blank substrate to corresponding solder contacts on a second surface of the substrate. The conductive layer electrically couples the solder lands.

Abstract: A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.

Abstract: Approaches for estimating power consumption of a circuit based on a circuit design. For one or more modules of the design, data are input that indicate measured power consumption and circuit resources used by the one or more modules. For one or more other parts of the design, values of parameters are input that specify an operating speed and a resource count. Process-corner, voltage, and temperature values are input. An estimated level of power consumption is determined as a function of the measured power consumption, the values of the parameters, and the values of the process-corner, voltage, and temperature. Data indicative of the estimated level of power consumption are output.

Abstract: An integrated circuit (IC) structure can include an internal element and a flexible circuitry directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure.

Abstract: A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed.

Abstract: A driver circuit of an integrated circuit is described. The driver circuit comprises a signal node coupled to receive an output signal of the integrated circuit; an inductor circuit having a resistor coupled in series with an inductor between a first terminal and a second terminal, wherein the first terminal is coupled to the signal node; an electro-static discharge protection circuit coupled to the second terminal of the inductor circuit; and an output node coupled to the second terminal of the inductor circuit. A method of generating an output signal is also disclosed.

Abstract: A method of assembling an integrated circuit package is disclosed. The method comprises placing a die on a substrate of the integrated circuit package; coupling a plurality of wire bonds from a plurality of bond pads on the die to corresponding bond pads on the substrate; applying a non-conductive material to the plurality of wire bonds; and encapsulating the die and the plurality of wire bonds. An integrated circuit package is also disclosed.

Abstract: Weight normalization in hardware or software without a division operator is described, using only right bit shift, addition and subtraction operations. A right bit shift is performed on an expected sum to effectively divide the expected sum by two to provide a first updated value for the expected sum. An iteration is performed which includes: incrementing with a first adder a first variable by the first updated value of the expected sum to provide an updated value for the first variable; subtracting with a first subtractor a second weight from a first weight to provide a first updated value for the first weight; and performing a left bit shift on the second weight to effectively multiply the second weight by two to provide a first updated value for the second weight.

Abstract: An embodiment of a method for a high-assurance operation is disclosed. For this embodiment of the method, a first processor and a second processor are clocked for lockstep operation. A first physical address and a first transaction request are provided to a shared bus from the first processor. A second physical address and a second transaction request are provided to the shared bus from the second processor. The first physical address, the first transaction request, the second physical address, and the second transaction request are passed to a proxy device coupled to the shared bus. The first processor and the second processor are proxy served by the proxy device including generation of a third transaction request and a third physical address by the proxy device.