Abstract: The present application provides a fan-out semiconductor packaging structure with an antenna module and a method making the same. The fan-out semiconductor packaging structure with the antenna module comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip; a filling structure disposed in the plastic packaging material layer and disposed on the periphery of the semiconductor chip, a loss caused by the filling structure to an antenna signal is smaller than a loss caused by the plastic packaging material layer to an antenna signal; an antenna module disposed on the first surface of the plastic packaging material layer, an orthographic projection of the antenna module on the filling structure is disposed on the filling structure; a redistribution layer disposed on the second surface of the plastic packaging material layer; and a solder bump disposed on a surface of the redistribution layer.

Abstract: A semiconductor package and an antenna module including the same includes a frame having first and second through-holes, a semiconductor chip disposed in the first through-hole of the frame and having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a wiring chip disposed in the second through-hole of the frame and including a body portion and a plurality of through vias penetrating the body portion, an encapsulant encapsulating at least portions of the semiconductor chip and the wiring chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and the through via of the wiring chip.

Abstract: A method of attaching a semiconductor die or chip onto a support member such as a leadframe comprises: applying onto the support member at least one stretch of ribbon electrical bonding material and coupling the ribbon material to the support member, arranging at least one semiconductor die onto the ribbon material with the ribbon material between the support member and the semiconductor die, coupling the semiconductor die to the ribbon material.

Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit-torque wiring which extends in a first direction; and a first ferromagnetic layer which is laminated in a second direction intersecting the spin-orbit-torque wiring, wherein the spin-orbit-torque wiring includes a convex portion which protrudes in the second direction in relation to a first surface on the side of the first ferromagnetic layer at a connecting part between the spin-orbit-torque wiring and the first ferromagnetic layer.

Abstract: A semiconductor device package is provided, which includes a carrier, a first reflective element, a second reflective element, a first optical component, a second optical component and a microelectromechanical system (MEMS) device. The carrier has a first surface. The first reflective element is disposed on the first surface of the carrier. The second reflective element disposed on the first surface of the carrier. The first optical component is disposed on the first reflective element. The second optical component is disposed on the second reflective element. The MEMS device is disposed on the first surface of the carrier to provide light beams to the first reflective element and the second reflective element. The light beams provided to the first reflective element are reflected to the first optical component and the light beams provided to the second reflective element are reflected to the second optical component.

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, a heat dissipation member attached to the inactive surface of the semiconductor chip and having a thickness greater than a thickness of the semiconductor chip, an encapsulant encapsulating at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member disposed on the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads, wherein the heat dissipation member is a complex of carbon and a metal.

Abstract: A semiconductor integrated optical device includes: a supporting base including semi-insulating semiconductor; a first photoelectric convertor having first photodiode mesas; a second photoelectric convertor having second photodiode mesas; a first 90° optical hybrid having at least one first multimode waveguide mesa; a second 90° optical hybrid having at least one second multimode waveguide mesa; an optical divider mesa; first and second input waveguide mesas coupling the first and second 90° optical hybrids with the optical divider mesa, respectively; a conductive semiconductor region disposed on the supporting base, the conductive semiconductor region mounting the first photodiode mesas, the second photodiode mesas, the first multimode waveguide mesas, the second multimode waveguide mesas, and the optical divider mesa; a first island semiconductor mesa extending between the first and second multimode waveguide mesas; and a first groove extending through the first island semiconductor mesa and the conductive

Abstract: A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.

Abstract: The present application provides an imaging assembly, a method and molding mold for fabricating same, a camera module, and a smart terminal. According to an aspect of the present application, the imaging assembly includes a photosensitive element and a molded encapsulation portion. The photosensitive element has a photosensitive area. The molded encapsulation portion is formed around the photosensitive area and is in contact with the photosensitive element. The molded encapsulation portion has an inclined inner side surface and a top surface higher than the photosensitive area. A height difference between the top surface of the molded encapsulation portion and the photosensitive area of the photosensitive element is less than or equal to 0.7 mm, and the inclined inner side surface and the top surface have different surface roughnesses.

Abstract: A method comprises depositing a barrier layer on a dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to an oxide present in the dielectric layer and depositing a doped liner layer on the barrier layer to bond with the metal layer to be deposited on the liner layer by the electroplating. The dopant forms a protective passivation layer on a surface of the liner layer and dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating bonds with the liner layer. The dopant reacts with the dielectric layer and forms a layer of a compound between the barrier layer and the dielectric layer. The compound layer prevents oxidation of the barrier layer and the liner layer due to the oxide present in the dielectric layer and adheres the barrier layer to the dielectric layer.

Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.

Abstract: A light-emitting diode (LED) device and a manufacturing method thereof are provided. The LED device includes a frame body, a first conductive extension structure, a second conductive extension structure, and a LED chip. The frame body includes an upper surface, a bottom, a recess on the opposite side of the bottom, and a first side surface and a second side surface opposite to each other. The first and second conductive extension structures are located in the frame body. The first and second conductive extension structures extend from the first side surface to the second side surface of the frame body. The frame body encapsulates a left side surface, a right side surface, a top surface, and a bottom surface of each of the first and second conductive extension structures. The LED chip is disposed in the recess and includes a first conductive pad and a second conductive pad.

Abstract: A memory device includes a memory stack formed on a substrate to program skyrmions within at least one layer of the stack. The skyrmions represent logic states of the memory device. The memory stack further includes a top and bottom electrode to receive electrical current from an external source and to provide the electrical current to the memory stack. A free layer stores a logic state of the skyrmions in response to the electrical current. A Dzyaloshinskii-Moriya (DM) Interaction (DMI) layer in contact with the free layer induces skyrmions in the free layer. A tunnel barrier is interactive with the DMI layer to facilitate detection of the logic state of the skyrmions in response to a read current. At least one fixed magnetic (FM) layer is positioned within the memory stack to facilitate programming of the skyrmions within the free layer in response to the electrical current.

Abstract: A method is provided that includes forming a memory cell that includes a memory element coupled in series with an isolation element. The isolation element includes a vertical thin-film transistor and a threshold selector device.

Abstract: A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.

Abstract: An operation method and an electronic device are provided. A proximity detection mode is activated in response to deactivating the display during an execution of a call application. In response to activating the proximity detection mode, a proximity distance of an object is identified based on outputting the light through the light emitting unit and receiving the light through the light receiving unit. If the identified proximity distance is larger than a pre-defined proximity recognition distance, the proximity detection mode is deactivated and the display is activated.

Abstract: An auxetic interposer includes: a frame enclosing an interior space; a pad arranged within the interior space; and a plurality of micro auxetic lattices extending between the frame and the pad.

Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.

Abstract: MEMS device, in which a body made of semiconductor material contains a chamber, and a first column inside the chamber. A cap of semiconductor material is attached to the body and forms a first membrane, a first cavity and a first channel. The chamber is closed on the side of the cap. The first membrane, the first cavity, the first channel and the first column form a capacitive pressure sensor structure. The first membrane is arranged between the first cavity and the second face, the first channel extends between the first cavity and the first face or between the first cavity and the second face and the first column extends towards the first membrane and forms, along with the first membrane, plates of a first capacitor element.

Abstract: A method for arraying micro-LED chips is disclosed. The method includes preparing a chip carrier formed with a plurality of chip pockets whose internal pressure is reduced through a plurality of suction holes, capturing the micro-LED chips in the corresponding chip pockets such that the micro-LED chips are in close contact with the bottoms of the chip pockets, and placing the micro-LED chips captured in the chip pockets on a base body. Each of the chip pockets includes a slope through which an inlet having a larger width than the bottom is connected to the bottom. The distances between the centers of the adjacent micro-LED chips placed on the base body are the same as those between the centers of the corresponding chip pockets.