Abstract: A method of manufacturing a light emitting device includes: providing a wiring substrate on which a light emitting element and a frame body surrounding the light emitting element are disposed, the frame body having a corner portion in a top view; forming a support column member in contact with at least one of an inner peripheral surface and a top surface of the corner portion of the frame body; and forming a light-transmissive member at least partially in contact with the frame body and the support column member with at least a part of the light-transmissive member being positioned above the frame body and the support column member.

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

Abstract: Reference marks for forming a staircase structure are disposed along slit areas of a 3D memory structure, and slits of the 3D memory structure are formed on the slit areas. In a staircase area, the reference marks are formed by etching the topmost one of stacked layers, having a pair of a dielectric layer and a sacrificial layer, in a stacked structure.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.

Abstract: A technique relates to a semiconductor device. A trench is formed in a space structured to accommodate at least two dummy gates in a cell, the space structured to accommodate the at least two dummy gates aligning to another two gates in another cell, the space further including an area previously occupied by a portion of fins. Dielectric material is formed in the space, such that the dielectric material in the space in the cell aligns to the another two gates in the another cell.

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

Abstract: A light emitting device includes: a substrate including a base member including an upper surface, a lower surface and one or more lateral surfaces, and defining a recess that is opened at the upper surface and the lateral surfaces and surrounds an outer perimeter of the upper surface; a first light emitting element; a second light emitting element; a light guide member covering the first and the second light emitting elements and the upper surface of the base member; and a first reflective member having a closed-ring shape surrounding the upper surface of the base member and the light guide member, a portion of the first reflective member being located in the recess. At least one of the lateral surfaces of the base member and corresponding at least one of one or more outer lateral surfaces of the first reflective member are in the same plane.

Abstract: A magnetic tunnel junction with out-of-plane magnetisation includes a storage layer; a reference layer; and a tunnel barrier layer. The two magnetisation states of the storage layer are separated by an energy barrier including a contribution due to the shape anisotropy of the storage layer and a contribution of interfacial origin for each interface of the storage layer. The storage layer has a thickness comprised between 0.8 and 8 times a characteristic dimension of a planar section of the tunnel junction. The contribution to the energy barrier due to the shape anisotropy of the storage layer is at least two times greater and preferably at least 4 times greater than the contributions to the energy barrier of interfacial origin.

Abstract: An electronic device is provided. The electronic device includes a fingerprint sensor including a sensor having a surface including epoxy molding compound (EMC) resin, a first layer disposed on the surface of the sensor or above the surface of the sensor, and a second layer disposed on the first layer or above the first layer. The first layer includes a first ultraviolet (UV) hardening material having first hardness. The second layer includes a second UV hardening material having second hardness greater than the first hardness and a surface of the second layer has surface roughness less than a specified value.

Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.

Abstract: A three-terminal avalanche photodiode provides a first controllable voltage drop across a light absorbing region and a second, independently controllable, voltage drop across a photocurrent amplifying region. The compositions of the absorbing region and the amplifying region may be optimized independently of each other. In the amplifying region, p-doped and n-doped structures are offset from each other both horizontally and vertically. Directly applying a voltage across a controlled region of the photocurrent path increases avalanche gain by shaping the electric field to overlap the photocurrent density. The resulting high-gain, low-bias avalanche photodiodes may be fabricated in integrated optical circuits using commercial CMOS processes, operated by power supplies common to mature computer architecture, and used for optical interconnects, light sensing, and other applications.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises forming on a substrate a mold structure including a plurality of sacrificial patterns and a plurality of dielectric patterns that are alternately stacked, patterning the mold structure to form a plurality of preliminary stack structures extending in a first direction, forming on the preliminary stack structures a support pattern that extends in a direction intersecting the first direction and extends across the preliminary stack structures, and replacing the sacrificial patterns with conductive patterns to form a plurality of stack structures from the preliminary stack structures. The support pattern remains on the stack structures.

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

Abstract: A photo-detecting apparatus includes a semiconductor substrate. A first germanium-based light absorption material is supported by the semiconductor substrate and configured to absorb a first optical signal having a first wavelength greater than 800 nm. A first metal line is electrically coupled to a first region of the first germanium-based light absorption material. A second metal line is electrically coupled to a second region of the first germanium-based light absorption material. The first region is un-doped or doped with a first type of dopants. The second region is doped with a second type of dopants. The first metal line is configured to control an amount of a first type of photo-generated carriers generated inside the first germanium-based light absorption material to be collected by the second region.

Abstract: The present application provides an imaging assembly, a method and molding mold for fabricating same, a camera module, and a smart terminal. According to an aspect of the present application, the imaging assembly includes a photosensitive element and a molded encapsulation portion. The photosensitive element has a photosensitive area. The molded encapsulation portion is formed around the photosensitive area and is in contact with the photosensitive element. The molded encapsulation portion has an inclined inner side surface and a top surface higher than the photosensitive area. A height difference between the top surface of the molded encapsulation portion and the photosensitive area of the photosensitive element is less than or equal to 0.7 mm, and the inclined inner side surface and the top surface have different surface roughnesses.

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.

Abstract: The present application provides a fan-out semiconductor packaging structure with an antenna module and a method making the same. The fan-out semiconductor packaging structure with the antenna module comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip; a filling structure disposed in the plastic packaging material layer and disposed on the periphery of the semiconductor chip, a loss caused by the filling structure to an antenna signal is smaller than a loss caused by the plastic packaging material layer to an antenna signal; an antenna module disposed on the first surface of the plastic packaging material layer, an orthographic projection of the antenna module on the filling structure is disposed on the filling structure; a redistribution layer disposed on the second surface of the plastic packaging material layer; and a solder bump disposed on a surface of the redistribution layer.

Abstract: A semiconductor package and an antenna module including the same includes a frame having first and second through-holes, a semiconductor chip disposed in the first through-hole of the frame and having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a wiring chip disposed in the second through-hole of the frame and including a body portion and a plurality of through vias penetrating the body portion, an encapsulant encapsulating at least portions of the semiconductor chip and the wiring chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and the through via of the wiring chip.

Abstract: A method of attaching a semiconductor die or chip onto a support member such as a leadframe comprises: applying onto the support member at least one stretch of ribbon electrical bonding material and coupling the ribbon material to the support member, arranging at least one semiconductor die onto the ribbon material with the ribbon material between the support member and the semiconductor die, coupling the semiconductor die to the ribbon material.

Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit-torque wiring which extends in a first direction; and a first ferromagnetic layer which is laminated in a second direction intersecting the spin-orbit-torque wiring, wherein the spin-orbit-torque wiring includes a convex portion which protrudes in the second direction in relation to a first surface on the side of the first ferromagnetic layer at a connecting part between the spin-orbit-torque wiring and the first ferromagnetic layer.