Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

Abstract: An electro-optical apparatus includes a first pixel and a second pixel. The first pixel and the second pixel include a reflective layer, an insulating layer, a functional layer, and an opposing electrode. The insulating layer includes a first insulating layer, a second insulating layer having a first opening, and a third insulating layer having a second opening. A first pixel electrode is provided on the first insulating layer in the first opening. A second pixel electrode is provided on the second insulating layer.

Abstract: A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.

Abstract: A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of vertical fins on a semiconductor substrate. The method further includes depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate. The method further includes forming a plurality of dummy gate structures over each of the vertical fins. The method further includes depositing a hardmask on the dummy gate. The method further includes depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins. The method further includes depositing a second dielectric layer on a portion of the spacer layer. The method further includes recessing spacer layer to expose a portion of the hardmask and the plurality of fins. The method further includes forming a source/drain region on the exposed portion of the plurality of fins.

Abstract: The disclosure concerns a semiconductor chip, which may be an interposer, having conductive through vias having a parallelepipedal shape.

Abstract: Provided is a semi-insulating crystal represented by a composition formula InxAlyGa1-x-yN (satisfying 0?x?1, 0?y?1, 0?x+y?1), wherein each concentration of Si, B, and Fe in the crystal is less than 1×1015 at/cm3, electric resistivity under a temperature condition of 20° C. or more and 200° C. or less is 1×106 ?cm or more.

Abstract: An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor.

Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Abstract: A method, comprising: providing a light emitting element including a semiconductor stack body and an electrode; providing a lightguide plate having a first surface and a second surface opposite to the first surface, wherein the second surface includes a plurality of recesses; arranging a light-transmitting member in each of the recesses; adjusting upper surfaces of the light-transmitting members to a uniform height; placing a wavelength conversion member on the light-transmitting member; placing the light emitting element on the wavelength conversion member with the electrode facing up; arranging a cover member that covers the light emitting element; removing the cover member until the electrode is exposed; and forming a wiring that electrically connects the light emitting elements together.

Abstract: A magnetic tunnel junction with out-of-plane magnetisation includes a storage layer; a reference layer; a tunnel barrier layer, the two magnetisation states of the storage layer being separated by an energy barrier, the magnetic tunnel junction having a thermal stability factor dependent on the energy barrier and on the temperature of use of the magnetic tunnel junction. The storage layer has a thickness comprised between 0.5 times and 8 times a characteristic dimension of a planar section of the tunnel junction; the composition and the thickness of the storage layer are chosen such that the absolute value of the derivative of the thermal stability factor compared to a characteristic dimension of a planar section of the tunnel junction is less than 10 nm?1.

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a connection pad. The redistribution circuit structure is located on and electrically connected to the semiconductor die. The connection pad is embedded in and electrically connected to the redistribution circuit structure, and the connection pad includes a barrier film and a conductive pattern underlying thereto, where a surface of the barrier film is substantially leveled with an outer surface of the redistribution circuit structure.

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

Abstract: An array substrate is provided that includes a plurality of sub-pixels arranged in a matrix. Each of the sub-pixels includes a substrate, a gate, a source and a drain, and a common electrode on the substrate, a passivation layer on a side of the common electrode facing away from the substrate, and a pixel electrode on a side of the passivation layer facing away from the substrate. The array substrate further includes a common electrode line, the common electrode line being formed of a same material in a same layer as the source and the drain. The common electrode is in direct electrical contact with the common electrode line. The pixel electrode and the drain are electrically connected through a via hole in the passivation layer. A display panel and a method for manufacturing an array substrate are further provided.

Abstract: An electronic device capable of being stretched from a first status to a second status includes a stretchable substrate stretchable in a stretching direction and a first pixel disposed on the stretchable substrate. The first pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel and the second sub-pixel arrange along a first direction when the electronic device is in the first status, and the first sub-pixel and the second sub-pixel arrange along a second direction when the electronic device is in the second status, wherein the first direction and the second direction form different angles with respect to the stretching direction.

Abstract: According to one embodiment, a light emitting module includes a first insulating film having optical transparency, a second insulating film arranged facing the first insulating film and having optical transparency, a conductor layer formed on the first insulating film, and a plurality of light emitting elements arranged between the first insulating film and the second insulating film and connected to the conductor layer in a first surface on one side. Each of the plurality of light emitting elements including a first electrode in which a height from a second surface opposite to the first surface is a first height and a second electrode in which a height from the second surface is a second height. The plurality of light emitting elements are arranged such that a distance between the first electrodes of adjacent light emitting elements is smaller than a distance between the second electrodes.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.

Abstract: A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.