Abstract: A semiconductor component (1a) has first and second insulated gate field effect devices (T1 and T2) formed within the same seminconductor body (2). The devices (T1 and T2) have a common first main electrode (D) and an arrangement (20) provides a resistive connection (20b) between a second main electrode (S2)of the second device (T2) and the insulated gate (G1) of the first device (T1). The second device (T2) is formed so as to be more susceptible than the first device (T1) to parasitic bipolar transistor action for causing, when the first and second devices (T1 and T2) are turned off and a voltage exceeding a critical voltage (V.sub.

Abstract: A light emitting diode including a carrier injection layer of semiconductor material, such as diamond, and a light emitting layer of electroluminescent organic material, such as PPV, positioned to form a diode junction therebetween. The semiconductor material being selected to have a wider bandgap than the organic material and the materials being further selected to minimize the discontinuities at the junction which would cause energy spikes.

Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of reflow solder joints between conductive bumps on the die and corresponding conductive bumps of the substrate. In one embodiment, conductive elements embedded in the preformed planar structures extend at least partially into the through holes, forming electrical connections with the corresponding solder joints. The conductive elements can be used to electrically connect one solder joint to another within the interposer, and/or may extend beyond an edge of the interposer to provide for electrical probing of or connection to the solder joints. In one embodiment, the conductive elements are extended outside of the preformed planar structure to form "pins" or leads of the flip-chip structure.

Abstract: Integrated semiconductor-on-insulator (SOI) sensors and circuits which are electrostatically bonded to a support substrate, such as glass or an oxidized silicon wafer, are disclosed. The SOI sensors and SOI circuits are both formed using a novel fabrication process which allows multiple preformed and pretested integrated circuits on a silicon wafer to be electrostatically bonded to the support substrate without exposing the sensitive active regions of the electronic devices therein to a damaging electric field. The process includes forming a composite bonding structure on top of the integrated circuits prior to the bonding step. This composite structure includes a conductive layer dielectrically isolated from the circuit devices and electrically connected to the silicon wafer, which is spaced form but laterally overlaps at least the active semiconductive regions of the circuit devices.

Abstract: There is provided a lead frame with enhanced adhesion to a polymer resin. The lead frame is coated with a thin layer of containing a mixture of chromium and zinc. A mixture of chromium and zinc with the zinc-to-chromium ratio in excess of about 4:1 is most preferred. The coated lead frames exhibit improved adhesion to a polymeric resin.

Abstract: An improved density semiconductor device having a novel buried interconnect is described. The buried interconnect electrically connects electrical device regions on a semiconductor substrate such that other structures may directly overlie the buried interconnect but not be electrically connected to the electrically conductive portions of the interconnect. The interconnect is composed of a buried conductor and conductive segments. The conductive segments are electrically joined to the buried conductor so as to form an electrical pathway. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. A nonconductive portion of selective poly-epi silicon is then formed over the buried conductor by oxidizing at least some of the selective poly-epi silicon layer.

Abstract: An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: An improved semiconductor device is disclosed having a predetermined amount of solder, or other electrically conductive binder adsorbed onto the exterior package leads of the semiconductor device. A de-wettable coating comprising preferably nickel, or alternatively chromium, is plated to a superior portion of the package leads, such that, when the heat is applied to the substrate mounting end of the leads, solder desorbes from the de-wettable layer and flows down the lead to the contact pads on the mounting substrate and forms a solder joint. The amount of solder delivered to the contact pad for joint formation is determined by the thickness of the adsorbed solder layer overlying each package lead. Only enough solder is provided on each lead sufficient to form the joint thus avoiding solder bridging between adjacent contact pads.

Abstract: For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n (n is natural numbers greater than or equal to 2) pitch.

Abstract: A pyroelectric IR-sensor in which a pyroelectric light receiving element is mounted on a MID substrate or a ceramic substrate of which thermal conductivity is less than 0.02 cal/cm.sec..degree. C. in a manner that both end portions of the pyroelectric light receiving element are supported by the substrate with the central portion of the pyloelectric light receiving element being spaced from the substrate, and chip parts are further mounted on the substrate.

Abstract: A method for manufacturing a semiconductor device using inclined stage of a dicing saw in order to cut the semiconductor substrate obliquely with respect to the depthwise direction. When a plurality of semiconductor chips diced obliquely are connected, a degree of connecting accuracy is increased, and it is possible to realize a contact-type image sensor of high resolving power and high accuracy.

Abstract: Disclosed is a method of manufacturing a semiconductor device in which an upper conductor layer and a lower conductor layer are electrically connected to each other through a contact hole provided in a multi-layer film. A lower conductor layer having a connection portion is formed on a semiconductor substrate. A first insulator film is formed on the semiconductor substrate to cover the lower conductor layer. On the first insulator film is formed a second insulator film having etching speed different from that of the first insulator film. An opening portion for exposing the connection portion is formed in the first and second insulator films. A native oxide film existing on the surface of the exposed opening portion is removed. An upper conductor layer is deposited on the second insulator film to fill the opening portion.

Abstract: A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.

Abstract: The present invention relates to a semiconductor device sealed by a resin and, more particularly, to a semiconductor device for reducing a production cost and effectively radiating heat generated from a semiconductor element. For this reason, a silicon chip in which an insulating layer is formed between the surface of the silicon chip and a conductive layer is arranged between a heat sink and a semiconductor element. The silicon chip insulates the semiconductor element from the heat sink and transmits heat generated from the semiconductor element to the heat sink. The silicon chip can be manufactured in a line for manufacturing the semiconductor element, and the silicon chip can be assembled with the semiconductor element.

Abstract: A semiconductor device includes a semiconductor element attached to a support member by a junction material that includes a parent phase of a low-melting-point junction material and fine particles of a high-melting-point junction material which are uniformly dispersed in the low-melting-point material. By heating the junction material to a temperature higher than the melting point of the low-melting-point junction material and lower than the melting point of the high-melting-point junction material, the low-melting-point junction material is brought to a molten state, making the entire junction material fluid. Thus, the size of the junction material need not be adjusted to that of the semiconductor element. Further, with this semiconductor device, the contact area between the low-melting-point junction material and the high-melting-point junction material is extremely large so that the requisite time for making the composition of the junction material uniform is shortened.

Abstract: An IGFET has a non-single crystalline semiconductor layer formed on an insulating surface of a substrate. In a first embodiment, the semiconductor layer is intrinsic n- or p- type and the concentration of oxygen, carbon, or nitrogen in the layer is not higher than 5.times.10.sup.18 atoms/cm.sup.3, source and drain regions are formed in the semiconductor layer by selectively doping with an n-type or p-type impurity and selectively crystallizing the doped portion, and a channel region between the source and drain includes a hydrogen or halogen element. In another embodiment, the semiconductor layer is doped with a dangling bond neutralizer and a P-, I, or N- type channel region is formed in the layer. and a part of the channel region near the source-channel and drain-channel boundaries is selectively crystallized. Alternatively, the source and drain regions may be selectively crystallized without crystallizing the source-channel and drain-channel boundaries.

Abstract: A semiconductor package device is disclosed. In one embodiment, attached by its active face to a lead-on-chip leadframe having leadfingers is an integrated circuit. The integrated circuit has a polyimide coating on its backside. An encapsulating material surrounds the integrated circuit and the lead-on-chip leadframe so that the leadfingers are exposed. The polyimide coating on the backside of the integrated circuit helps to reduce package cracking arising from mounting the device to a printed circuit board by relflow solder.

Abstract: A first, lower heat sink disposed immediately below and closely adjacent a semiconductor chip (die) in a semiconductor chip assembly is disclosed. The lower heat sink is a flat metallic or ceramic shim. A second, upper heat sink disposed immediately above and closely adjacent the top surface of the semiconductor device is disclosed. The upper heat sink may have a portion in contact with a passivation layer over the top surface of the semiconductor die (device). The second heat sink preferably has a flat surface forming an exterior surface of the semiconductor device assembly. In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications wherein the semiconductor chip assembly is mounted to a thermal mass.

Abstract: A lead frame for a semiconductor device includes a resin base film having opposed surfaces and an opening therein. A plurality of inner leads are formed of a metal foil on one surface of the film in a desired inner lead circuit pattern that includes inner edges arranged for connection to a semiconductor device mounted on the film and outer edges positioned over the opening. A plurality of outer leads are formed of a metal sheet and adhered to the other surface of the film in a desired outer lead circuit pattern that includes inner edges positioned over the opening and outer edges that extend outwardly from the frame.

Abstract: A method for forming an improved bonding pad structure. A bond pad structure is formed by depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and conductive layer are then patterned and etched to define a conductive region. In a preferred embodiment, the conductive region is formed in the shape of a grid. A second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.