Abstract: A circuit arrangement for a power semiconductor module provides low parasitic inductances and low loss. An electrically insulating substrate supports metallic ribbon connectors which in turn power attached semiconductor components. DC port conducts are positioned in close proximity to each other and are arranged in at least one partial sector parallel and in close proximity to the surface of the substrate and/or the ribbon connectors and electrically insulated from the same, and at least one AC port conductor is similarly attached. The port conductors include surface elements enabling simplified low-inductance wire bond connection from the port conductors to either the power semiconductor components or ribbon connectors or both.

Abstract: A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, and the land section includes a first section which is in contact with the underlayer, and a second section which is not in contact with the underlayer.

Abstract: An electronic structure includes an electronic device coupled to a substrate by conductive bumps and ball limiting metallurgy (BLM). Underfill material having filler particles is disposed in a space between the electronic device and the substrate. A weight percentage of the filler particles is at least about 60%. A particle size of at least 90 wt % of the filler particles is less than about 2 ?m and/or the filler particles are coated by an organic coupling agent. Once the underfill material is fully cured, its coefficient of thermal expansion is no more than 30 PPM/° C., and its glass transition temperature is at least 100° C., and its adhesion to a passivation layer of the electronic device, to the substrate and to the electronic device at its edges is such that the electronic structure passes standardized reliability tests without delamination of the ball limiting metallurgy.

Abstract: A stacked-type semiconductor device includes a first wiring substrate on which a semiconductor device element is mounted, a second wiring substrate stacked on the first wiring substrate through a plurality of electrode terminals which are electrically connected with the first wiring substrate, and a conductor supporting member disposed around the semiconductor device element, and connected with grounding wiring layers provided in the first and second wiring substrate.

Abstract: A multi-die module is electrically connected to both an unpackaged die and a packaged die as disclosed herein. The multi-die module has a footprint that is the same as conventional multi-die packages, which do not include packaged die, thereby allowing the multi-die module to be interchangeable with conventional multi-die packages. In one embodiment, the unpackaged die is a graphics processor, and the packaged die is a standard memory that has been burned in, functionally tested, and speed rated.

Abstract: Disclosed is a land grid array module comprising: a substrate; a plurality of active and passive components mounted on both sides of the substrate; and a molding compound for encapsulating the both sides of the substrate with the active and passive components mounted thereon. The land grid array module mounts the passive and active components on both sides of the substrate, thereby improving the integration of the circuit device. Also, the use of a thin film printed circuit board or a flexible printed circuit board with high rigidity as the substrate reduces the overall thickness of the land grid array module.

Abstract: Die pads 50, 51, an external connecting electrode 52 and a bridge are covered with an insulating resin after half-etching, formed into a single package without a coupling member such as a supporting lead or adhesive tape. In addition, since no supporting board is required, a low-profile semiconductor device with improved heat radiation can be provided.

Abstract: An integral-detem-type optical semiconductor device employing lead frame(s) 11, shield case region(s) 111 created by bending portion(s) of lead frame(s) 11 extending to the exterior being disposed between light-emitting lens portion(s) 19 and light-receiving lens portion(s) 18 of resin package(s) 17 produced as a result of encapsulation by translucent resin(s).

Abstract: A semiconductor device has peripheral electrode pads formed on the periphery of a semiconductor chip, land pads comprising the first land pads and the second land pads formed on the semiconductor chip, and circuits formed in the semiconductor chip. The peripheral electrode pads are connected to internal circuits by internal lines. The first land pads are connected to the peripheral electrode pads by rewired lines. The second electrode pads, on the other hand, are connected to the internal circuits by internal electrode pads and internal lines, not by the peripheral electrode pads.

Abstract: A multi-chip circuit module on which semiconductor chips are loaded and which is provided with circuit patterns, input/output terminals or the like for interconnecting the semiconductor chips. A multi-layered wiring section (2) is formed by respective unit wiring layers (8) to (12) in such a manner that an upper unit wiring layer is layered on a surface-planarized subjacent unit wiring layer and connected to one another by inter-layer connection by a via-on-via structure. A semiconductor chip (6) mounted on this multi-layer wiring section (2) is polished along with the sealing resin layer (7) for reducing the thickness.

Abstract: A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the semiconductor chip opposite from the solid device.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

Abstract: An embedded heat spreader includes a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally conductive substrate attached to the polymer resin such that the thermally conductive substrate can spread heat from the semiconductor die.

Abstract: A method of forming a heat spreader ball grid array package, and the resultant heat spreader ball grid array package, comprising the following steps. A semiconductor chip affixed to a ball grid substrate is provided. The semiconductor chip over the ball grid substrate is encased with a molding compound. A heat spreader is mounted over the ball grid substrate and spaced apart from the molding compound to form a gap. Thermal grease is placed into the gap, at least between the heat spreader and the molding compound, to form the heat spreader ball grid array package. It is also possible to place thermal grease over the molding compound and then mounting the heat spreader over the ball grid substrate.

Abstract: On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.

Abstract: A flip-chip package includes a packaging substrate; an integrated circuit die affixed to the packaging substrate, wherein the integrated circuit die includes an active integrated circuit surrounded by a peripheral die seal ring therein; and a thermal stress releasing pad disposed in a stress-releasing area that is at a corner of the integrated circuit die outside the die seal ring, wherein the thermal stress releasing pad is connected to the packaging substrate by using a solder bump, which, in turn, is connected to a dummy heat-spreading metal plate embedded in the packaging substrate so as to form a heat shunting path for reducing thermal stress during temperature cycling test.

Abstract: An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. The invention also includes semiconductor devices that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention. Specifically, the present invention includes semiconductor devices including doped silicon oxide structures with substantially vertical sidewalls and adjacent undoped silicon oxide or silicon nitride structures exposed adjacent the sidewall.

Abstract: An optical semiconductor device includes a first set of lead frames having a first set of element mounting beds, a second set of lead frames having a second set of element mounting beds, which are arranged substantially on a same plane as the first set of element mounting beds. A light-emitting element is mounted on one of the first set of element mounting beds and having a pair of electrodes connected to the first set of lead frames respectively. A light-receiving element is arranged at a position facing to the light-emitting element and having a pair of electrodes connected to the second set of lead frames respectively. A supporting means is mounted on the second set of element mounting beds for supporting the light-receiving element at the position facing to the light-emitting element and for receiving a light emitted from the light-emitting element.