Patents Examined by Chuong A Luu
  • Patent number: 10446750
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 15, 2019
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10438997
    Abstract: The present invention is directed to a magnetic structure including a first seed layer, which is made of a first transition metal, formed on top of a second seed layer comprising cobalt, iron, and boron; and a magnetic fixed layer structure formed on top of the first seed layer and having a first invariable magnetization direction substantially perpendicular to a layer plane thereof. The magnetic fixed layer structure includes layers of a first magnetic material interleaved with layers of a second transition metal. The first transition metal may be chromium or iridium. The second transition metal may be nickel, platinum, palladium, or iridium. The second seed layer which comprises cobalt, iron, and boron, may have a noncrystalline structure. Moreover, the second seed layer may be non-magnetic or superparamagnetic. The magnetic structure may further includes a third seed layer, which may comprise tantalum, formed adjacent to the second seed layer opposite the first seed layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 8, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 10439004
    Abstract: The present invention mainly discloses a high-efficiency OLED device, comprising: an anode substrate, a hole transport layer (HTL), at least one emission layer (EML), an electron transport layer (ELT), and a cathode layer. In this high-efficiency OLED, LUMO level of the HTL, LUMO level of the EML and LUMO level of the ETL together form a step-like LUMO level, and HOMO level of the HTL, HOMO level of the EML and HOMO level of the ETL also constitute one step-like HOMO level. On the other hand, the electron mobility of the ETL is greater than the EML's electron mobility by at least 2 orders in this high-efficiency OLED. Moreover, a variety of experimental data have proved that, a specific OLED would certainly exhibits outstanding luminance performance as long as the specific OLED is made based on the above-mentioned physical characteristics limitations for the ETL, the EML and the HTL.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 8, 2019
    Assignee: National Tsing Hua University
    Inventor: Jwo-Huei Jou
  • Patent number: 10431734
    Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Jimmy Jianan Kan, Peiyuan Wang, Seung Hyuk Kang
  • Patent number: 10431754
    Abstract: Disclosed is a flexible display device that includes a display element that is flexible; and a member that is located on a surface of the display element and is made of a material having a 3-dimensional cross-linked structure. The display element has an original shape and has an elastic modulus that enables the display element to flex into a modified shape. The member has a rigidity that urges the display element from the modified state back to the original shape.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 1, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Kazuhiko Tamai
  • Patent number: 10424621
    Abstract: The invention provides a manufacturing method for white OLED device, comprising manufacturing a first OLED device and a corresponding second OLED device respectively on a first substrate and a second substrate, wherein the light emitted by the first OLED device and the light emitted by the second OLED device are mixed to form white light, and then the second OLED device is correspondingly stacked onto the first OLED device to obtain a white OLED device. The manufacturing method can greatly reduce the complicated process caused by layer-by-layer stacking of multi-layered films in the structure of known white OLED devices, without the need to address the complex issues caused by interlinking of multiple color devices and light color resonance, so as to greatly simplify the process.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 24, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Youyuan Kuang
  • Patent number: 10424539
    Abstract: A wiring structure includes a main body, a first dielectric layer, a first circuit layer and a second dielectric layer. The first dielectric layer is disposed on the main body, and defines a plurality of first grooves and at least one receiving portion between two first grooves. The first circuit layer is disposed on the first dielectric layer, and includes at least one first conductive trace disposed on the receiving portion. A width of the first conductive trace is less than a width of the receiving portion. A second dielectric layer disposed on the first dielectric layer, and extends into the first grooves.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Ching Kuo Hsu
  • Patent number: 10424615
    Abstract: A display panel including a backplane, a first bonding layer, a plurality of micro light-emitting diodes, a first insulation layer, and a second bonding layer is provided. The first bonding layer is disposed on the backplane. The micro light-emitting diodes are disposed on the first bonding layer and are electrically connected to the first bonding layer. The first insulation layer is located between any adjacent two of the micro light-emitting diodes. The first insulation layer has a concave-convex surface. The second bonding layer is disposed on the micro light-emitting diodes and the first insulation layer and is electrically connected to the micro light-emitting diodes. A micro light-emitting diode apparatus including a substrate, a plurality of micro light-emitting diodes, and a first insulation layer is provided. The first insulation layer is located between any adjacent two of the micro light-emitting diodes. The first insulation layer has a concave-convex surface.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 24, 2019
    Assignee: PlayNitride Inc.
    Inventors: Chih-Ling Wu, Yu-Hung Lai, Yi-Min Su, Yu-Yun Lo, Tzu-Yang Lin
  • Patent number: 10424575
    Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: September 24, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
  • Patent number: 10418359
    Abstract: A semiconductor device 100 includes a semiconductor element 12 having an electrode on a front surface, a wire 15 bonded to the electrode of the semiconductor element 12, a resin layer 22b covering a bonding portion of the wire 15 on the front surface of the semiconductor element 12, and a gel filler material 23 that seals the semiconductor element 12, the wire 15, and the resin layer 22b. By protecting the bonding portion of the wire 15 with the resin layer 22b, degradation of the wire 15 is ameliorated and the reliability of the semiconductor device 100 is improved.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Kanai, Motohito Hori, Satoshi Kaneko
  • Patent number: 10418272
    Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Garo Jacques Derderian, Hui Zang, John Zhang, Haigou Huang, Jinping Liu
  • Patent number: 10410943
    Abstract: A system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a reactor, exposing the surface of the semiconductor to a gas-phase metal containing precursor in the reaction chamber and exposing the surface of the semiconductor to a gas-phase chalcogenide containing precursor. The methods also include passivating the surface of the semiconductor using the gas-phase metal containing precursor and the gas-phase chalcogenide containing precursor to form a passivated surface.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: September 10, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Xiaoqiang Jiang, Fu Tang, Qi Xie, Pauline Calka, Sung-Hoon Jung, Michael Eugene Givens
  • Patent number: 10410901
    Abstract: An electrostatic chuck table includes a plate-shaped base portion capable of transmitting a laser beam to be applied to a workpiece and an electrostatic attraction electrode portion capable of transmitting the laser beam. The laser beam has a transmission wavelength to the workpiece. The base portion has a first surface and a second surface opposite to the first surface. The electrode portion is formed on the first surface of the base portion. A method for using the electrostatic chuck table includes a workpiece holding step of applying a voltage to the electrode portion formed on the first surface to thereby electrostatically hold the workpiece on the second surface, and a modified layer forming step of applying the laser beam through the first surface to a predetermined position inside the workpiece held on the second surface to thereby form a modified layer inside the workpiece.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 10, 2019
    Assignee: DISCO CORPORATION
    Inventors: Kenji Furuta, Yuriko Sato, Sakae Matsuzaki
  • Patent number: 10403596
    Abstract: A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of conducive vias that penetrate the dielectric layer, an electronic component disposed on the first surface of the dielectric layer and electrically connected to the wiring layer, an encapsulant encapsulating the electronic component, and a packaging substrate disposed on the second surface and electrically connected to the conductive vias. With the dielectric layer in replacement of a conventional silicon board and the wiring layer as a signal transmission medium between the electronic component and the packaging substrate, the package structure does not need through-silicon vias. Therefore, the package structure has a simple fabrication process and a low fabrication cost. The present invention further provides a method of fabricating the package structure.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Indsutries Co., Ltd.
    Inventors: Hsien-Wen Chen, Shih-Ching Chen, Chieh-Lung Lai
  • Patent number: 10403567
    Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Mu-Hsuan Chan, Chieh-Yuan Chi
  • Patent number: 10396280
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shinji Mori, Masayuki Tanaka, Kazuhiro Matsuo, Kenichiro Toratani, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Yuta Saito
  • Patent number: 10396011
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 27, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10381329
    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 10381404
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate having a buried insulator layer and an active layer overlying the buried insulator layer. A transistor overlies the buried insulator layer, and a memory cell underlies the buried insulator layer. As such, the memory cell and the transistor are on opposite sides of the buried insulator layer.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bhushan Bharat, Juan Boon Tan, Danny Pak-Chum Shum, Yi Jiang, Wanbing Yi
  • Patent number: 10374083
    Abstract: A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu