Abstract: A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

Abstract: The present disclosure relates to a semiconductor device, a manufacturing method of the semiconductor device, and electronic equipment that are directed to improving quality and reliability of a semiconductor device including a through electrode, or electronic equipment. The semiconductor device includes a first semiconductor substrate including a through electrode, a first insulating film laminated on a first surface of the first semiconductor substrate, and a second insulating film laminated on the first insulating film, in which an inner wall and a bottom surface of the through electrode are covered with a conductor, the first insulating film and the second insulating film are laminated on the conductor, and the through electrode includes a groove which reaches the first insulating film on the bottom surface from the first surface of the first semiconductor substrate. The present technology may be applied to a packaged solid-state imaging device or the like, for example.

Abstract: There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.

Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

Abstract: A nonvolatile memory cell using vertical nanowire (VNW) FETs includes a program element of which a gate is connected to a word line, and a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line. The program element and the switch element are each constituted by one or a plurality of VNW FETs, and these VNW FETs are arranged in a line in a first direction.

Abstract: A semiconductor device includes a first high resistance pattern and a second high resistance pattern that are disposed along an X axis and are separated from each other, a coupling pattern that couples the first high resistance pattern and the second high resistance pattern, and a signal wiring disposed at a layer above the first high resistance pattern, the second high resistance pattern, and the coupling pattern. The coupling pattern includes a first portion that overlaps an end portion of the first high resistance pattern in a plan view at the layer above the first high resistance pattern, the coupling pattern includes a second portion that overlaps an end portion of the second high resistance pattern in a plan view at a layer above the second high resistance pattern, and the signal wiring is disposed along a Y axis that intersects the X axis in a plan view between an end of the coupling pattern at the first portion side and an end of the coupling pattern at the second portion side.

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a first source electrode, a first gate electrode, a first drain electrode, a source pad part, a first source connection part, and an insulating part. The semiconductor member includes first and second semiconductor layers. The first gate electrode includes first to fourth portions. The first source electrode is between the first and second portions in a first direction, and is between the third and fourth portions in a second. The first drain electrode extends along the first direction. The first source electrode is between the third portion and the first drain electrode in the second direction. The first source connection part electrically connects the first source electrode and the source pad part. A portion of the first insulating region of the insulating part is between the first portion and the first source connection part.

Abstract: A semiconductor device includes a substrate, having a silicon layer on top. A device structure is disposed on the substrate. A dielectric layer is disposed on the substrate and covering over the device structure. The dielectric layer has a first air gap above the device structure. The first air gap is enclosed by a dielectric wall constituting as a part of the dielectric layer and the dielectric wall is disposed on the device structure. The dielectric layer has a second air gap, exposing a top of the device structure and adjacent to the dielectric wall.

Abstract: A semiconductor device includes a semiconductor part having a recess formed in an upper surface thereof, an insulating member provided in a portion of the recess, a first electrode, a gate insulating film thinner than the insulating member. The first electrode includes a first part provided in another portion of the recess, and a second part provided higher than the insulating member. The gate insulating film is provided between the semiconductor part and the first part. The semiconductor part includes a first layer of a first conductivity type contacting the gate insulating film, second and third layers of a second conductivity type contacting the first layer and being connected to a source contact and a drain contact. The recess is positioned between the source contact and the drain contact when viewed from above. The insulating member is provided between the first part and the third layer.

Abstract: To reduce the capacitance between wiring lines of a semiconductor device, while maintaining mechanical strength and reliability. A semiconductor device including: a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion preventing films are alternately stacked, and a wiring line is formed in the interlayer films; a contact via that penetrates a via insulating layer formed on one surface of the multilayer wiring layer, and is electrically connected to the wiring line of the multilayer wiring layer; a through hole that penetrates at least one of the interlayer films and the diffusion preventing films from the other surface of the multilayer wiring layer on the opposite side from the one surface; and an air gap that is connected to the through hole, and is formed in at least one of the interlayer films, to expose the contact via.

Abstract: A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.

Abstract: A method for fabricating thin-film optoelectronic devices (100), the method comprising: providing a alkali-nondiffusing substrate (110), forming a back-contact layer (120); forming at least one absorber layer (130) made of an ABC chalcogenide material, adding least one and advantageously at least two different alkali metals, and forming at least one front-contact layer (150) wherein one of said alkali metals comprise Rb and/or Cs and where, following forming said front-contact layer, in the interval of layers (470) from back-contact layer (120), exclusive, to front-contact layer (150), inclusive, the comprised amounts resulting from adding alkali metals are, for Rb and/or Cs, in the range of 500 to 10000 ppm and, for the other alkali metals, typically Na or K, in the range of 5 to 2000 ppm and at most ½ and at least 1/2000 of the comprised amount of Rb and/or Cs.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concentration than the dopant concentration in the second well.

Abstract: A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular interposer disposed over the substrate and surrounding the stack of semiconductor dies. The annular interposer can include a plurality of circuit elements each electrically coupled to at least a corresponding one of the plurality of electrical contacts. The package can further include a lid disposed over the annular interposer and the stack of semiconductor dies.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a silicon-containing gate electrode, and at least two gate silicide strips. The silicon-containing gate electrode is on the semiconductor substrate. The at least two gate silicide strips are on an upper surface of the silicon-containing gate electrode.

Abstract: A method for forming semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the gate stack. The method also includes forming a dielectric layer over the semiconductor substrate to surround the gate stack and the spacer element and replacing the gate stack with a metal gate stack. The method further includes forming a protection element over the metal gate stack and forming a conductive contact partially surrounded by the dielectric layer. A portion of the conductive contact is formed directly above a portion of the protection element.

Abstract: The present disclosure provides an integrated circuit structure with dielectric isolation structure for reducing capacitive coupling and crosstalk between conductive features and a method for preparing the same.