Patents Examined by Fernando Hidalgo
  • Patent number: 11495285
    Abstract: Apparatuses and methods for signal line buffer timing control are disclosed. An example apparatus includes a plurality of signal lines including first and second control lines and further including data lines, and further includes first and second signal line buffers. The first signal line buffer includes first driver circuits configured to drive respective data signals on the data lines and to drive first and second control signals on the first and second control lines, respectively. The second signal line buffer includes second driver circuits configured to be activated to receive the data signals. The first and second control signals arrive at the second signal line buffer at different times. The second driver circuits are activated responsive a later one of active first and second control signals and are deactivated responsive to an earlier one of inactive first and second control signals.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Keisuke Fujishiro, Yoshifumi Mochida
  • Patent number: 11488675
    Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: November 1, 2022
    Assignee: Kioxia Corporation
    Inventor: Tetsuaki Utsumi
  • Patent number: 11482272
    Abstract: An electronic device and a semiconductor package structure are provided. The device includes a plurality of semiconductor dies stacked vertically over each other and a power supply system. The semiconductor dies are stacked over the power supply system. The power supply system includes: a voltage generating circuit configured to generate at least one voltage. The at least one voltage is provided to the plurality of semiconductor dies through a power interconnecting structure. The semiconductor package structure includes a package substrate; at least one semiconductor die disposed on the package substrate; and the power supply system disposed on the package substrate. The at least one semiconductor die may include a plurality of semiconductor dies vertically stacked on the package substrate.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 25, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Shu-Liang Ning
  • Patent number: 11482264
    Abstract: The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 25, 2022
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Maha Kooli, Roman Gauchi, Pascal Vivet
  • Patent number: 11475932
    Abstract: A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: October 18, 2022
    Assignee: Sony Group Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 11475927
    Abstract: The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 18, 2022
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Xueqing Li, Yiming Chen, Xiaoyang Ma, Mufeng Zhou, Yushen Fu, Yongpan Liu, Huazhong Yang
  • Patent number: 11475955
    Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: October 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junha Lee, Seonkyoo Lee, Jeongdon Ihm, Byunghoon Jeong
  • Patent number: 11468955
    Abstract: An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 11, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11462279
    Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: October 4, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amiya Banerjee, Vinayak Bhat, Harish R. Singidi
  • Patent number: 11430513
    Abstract: A low voltage forming NVM structure including a plurality of ReRAM devices arranged in a cross bar array and sandwiched between a plurality of first electrically conductive structures and a plurality of second electrically conductive structures. Each first electrically conductive structure is oriented perpendicular to each second electrically conductive structure. The plurality of second electrically conductive structures includes a first set of second electrically conductive structures having a first top trench area A1, and a second set of second electrically conductive structures having a second top trench area A2 that is greater than A1. Each second electrically conductive structure of the first set contacts a surface of at least one of the first electrically conductive structures, and each second electrically conductive structure of the second set contacts a top electrode of at least one of the ReRAM devices.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 30, 2022
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Youngseok Kim, Dexin Kong, Takashi Ando, Hiroyuki Miyazoe
  • Patent number: 11430503
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: August 30, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Homare Sato
  • Patent number: 11423989
    Abstract: A processing device establishes a first data group of memory cells of a memory sub-system and a second data group of memory cells of the memory sub-system. A first portion of the first data group is programmed at a threshold voltage level to set a first embedded data value. A second portion of the second data group of memory cells is programmed at the threshold voltage level offset by an offset voltage level to set a second embedded data value.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Michael Sheperek, Larry J. Koudele
  • Patent number: 11423706
    Abstract: The real-time data acquisition and recording data sharing system works in conjunction with a real-time data acquisition and recording system and a viewer which provides real-time, or near real-time, access to a wide range of data, such as event and operational data, video data, and audio data to remotely located users such as asset owners, operators and investigators. The data sharing system allows the user to share data obtained from the data acquisition and recording system to remotely located users. The user can share data with remote recipient end users that have internet access and a modern web browser in a secure, controlled, tracked, and audited way. The user, instead of sharing files, shares a URL to the data. URL based data sharing enables the user to control, track, and audit sensitive data. The user will be able to share data to improve the safety of the world's transportation systems without fear of unauthorized data dissemination.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: August 23, 2022
    Assignee: Wi-Tronix, LLC
    Inventors: Lawrence B. Jordan, Divya Dinesh, Matthew D. Hamsmith, Dan Alwin
  • Patent number: 11423966
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11423978
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 11423974
    Abstract: A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Patent number: 11417380
    Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11417375
    Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Jin Seung Son, Andrea Ghetti
  • Patent number: 11409674
    Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Vaughn N. Johnson, Kyle Alexander, Gary L. Howe, Brian T. Pecha, Miles S. Wiscombe
  • Patent number: 11403562
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache by training a machine learning module. A machine learning module that receives as input performance attributes of system components affected by staging tracks from the storage to the cache and outputs a staging strategy comprising one of a plurality of staging strategy indicating at least one of a plurality of sectors of a track to stage into the cache. A margin of error is determined based on a current value of a performance attribute and a threshold of the performance attribute. An adjusted staging strategy is determined based on the margin of error. The machine learning module is retrained with current performance attributes to output the adjusted staging strategy.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 2, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash