Abstract: A semiconductor device and a circuit are provided. The semiconductor device includes a substrate, a first gate structure, a first doped region, and a capacitor structure. The substrate includes a first well region having a first conductive type. The first gate structure is disposed on the substrate. The first doped region is in the substrate and has a second conductive type different from the first conductive type. The first gate structure and the first doped region are included in a first transistor. The capacitor structure includes a first electrode electrically coupled to the first doped region. The second doped region is in the substrate and has the second conductive type. The second doped region is electrically coupled to the first electrode of the capacitor structure and the first doped region.

Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

Abstract: A computer platform is disclosed. The computer platform comprises a non-volatile memory to store fuse override data; and a system on chip (SOC), coupled to the non-volatile memory, including a fuse memory to store fuse data and security micro-controller to receive the fuse override data and perform a fuse override to overwrite the fuse data stored in the fuse memory with the fuse override data.

Abstract: A programmable logic circuit includes multiple logic blocks that are connected communicatively, wherein multiple modules are reconfigured in any of the logic blocks, and wherein the modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory.

Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

Abstract: A magnetic tunnel junction is provided. The magnetic tunnel junction comprises an insulating tunnel barrier and a fixed ferromagnet layer adjacent the tunnel barrier. The fixed ferromagnet comprises a fixed magnetization along an easy axis approximately normal to an interface between the fixed ferromagnet and the tunnel barrier. A free ferromagnet layer is adjacent the tunnel barrier on the side opposite the fixed ferromagnet. The free ferromagnet layer comprises a bistable magnetization along the easy axis that can switch between a parallel state and an anti-parallel state with the fixed ferromagnet. A heavy metal layer is adjacent the free ferromagnet on the side opposite the tunnel barrier. A unidirectional electric current pulse through the heavy metal layer switches the bistable magnetization of the free ferromagnet, thereby switching an electrical resistance state of the magnetic tunnel junction.

Abstract: A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

Abstract: A memory device includes plural non-volatile memory cells and a control circuit. The plural non-volatile memory cells can store data and are arranged in series between a bit line and a source line. The control circuit synchronizes discharge of charges, which are accumulated in a channel formed by the plural non-volatile memory cells, through the bit line and the source line during an erase operation for erasing the data stored in the plural non-volatile memory cells.

Abstract: A semiconductor device includes: a first memory block having a first block pitch; and a second memory block belonging to a same plane as the first memory block, the second memory block located closer to a plane edge than the first memory block, the plane edge being an edge of the plane, wherein the second memory block has a second block pitch that is larger than the first block pitch.

Abstract: In a method of reducing reliability degradation of a nonvolatile memory device, the nonvolatile memory device in which initial data having an initial threshold voltage distribution is stored in a plurality of memory cells connected to a plurality of wordlines is provided. Before a first process causing reliability degradation is performed, a first write operation is performed such that first data having a first threshold voltage distribution is stored into memory cells connected to first wordlines. The first wordlines have a degree of reliability degradation less than a reference value. Before the first process is performed, a second write operation is performed such that second data having a second threshold voltage distribution is stored into memory cells connected to second wordlines. The second wordlines have a degree of reliability degradation greater than or equal to the reference value.

Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

Abstract: Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.

Abstract: A processing-in-memory (PIM) system includes a first and second PIM devices and a host. Each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators and a plurality of memory banks supplying weight data to the plurality of MAC operators. The host controls the first and second PIM devices and includes a data buffer. The first and second PIM devices include a first global buffer and a second global buffer, which supply the vector data to the plurality of MAC operators, respectively. The host reads the vector data out of the first and second PIM devices to store the vector data into the data buffer and writes the vector data stored in the data buffer into the first and second global buffers.

Abstract: A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.

Abstract: An electronic device may include: a clock divider circuit configured to generate a first internal clock including pulses which are generated in synchronization with odd pulses of a clock, and generate a second internal clock including pulses which are generated in synchronization with even pulses of the clock; and a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command/address signal for performing a precharge operation in synchronization with the first internal clock or toggled by the chip selection signal and the command/address signal for performing the precharge operation in synchronization with the second internal clock.

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

Abstract: A memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line. A first word line is connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates. A second word line is connected to gate conductors of the first and second pMOS pass gates in the first and second transmission gates.