Patents Examined by Hoa B. Trinh
  • Organic electroluminescent element
    Patent number: 9960363
    Abstract: The present invention provides an organic electroluminescent element which comprises: an anode; a cathode; and an organic layer interposed between the anode and the cathodes, wherein the organic layer comprises one or more types of layer from the group consisting of a hole-injection layer, hole-transport layer, light-emitting layer, lifetime enhancement layer, electron-transport layer, and electron-injection layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 1, 2018
    Assignee: DOOSAN CORPORATION
    Inventors: Min-Sik Eum, Ho-Cheol Park, Chang Jun Lee, Tae Hyung Kim, Jiyi Kim, Youngmi Beak
  • Process for fabricating semiconductor nanowires or microwires having insulated roots
    Patent number: 9954141
    Abstract: A process for fabricating an electronic device including a substrate and microwires or nanowires resting on the substrate, the process including successive steps of covering the wires with an insulating layer, covering the insulating layer with an opaque layer, depositing a first photoresist layer over the substrate between the wires, etching the first photoresist layer over a first thickness by photolithography, etching the first photoresist layer remaining after the preceding step over a second thickness by plasma etching, etching the portion of the opaque layer not covered by the first photoresist layer remaining after the preceding step, etching the portion of the insulating layer not covered by the opaque layer, removing the first photoresist layer remaining after the preceding step, and removing the opaque layer.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: April 24, 2018
    Assignees: Aledia, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Eric Pourquier, Philippe Gibert, Brigitte Martin
  • Chip package structure and manufacturing method thereof
    Patent number: 9947551
    Abstract: A chip package structure and the manufacturing method thereof are provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 17, 2018
    Assignees: NIKO SEMICONDUCTOR CO., LTD., SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Chih-Cheng Hsieh, Hsiu-Wen Hsu
  • Wafer-level package with at least one input/output port connected to at least one management bus
    Patent number: 9934179
    Abstract: A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.
    Type: Grant
    Filed: February 14, 2016
    Date of Patent: April 3, 2018
    Assignee: MEDIATEK INC.
    Inventor: Yao-Chun Su
  • Electronic device including a metal substrate and a semiconductor module embedded in a laminate
    Patent number: 9935027
    Abstract: An electronic device having a substrate including a metal layer, an electrically insulating layer disposed above the substrate, a semiconductor module disposed above the electrically insulating layer and a lamination layer disposed above the electrically insulating layer. The lamination layer at least partially embeds the semiconductor module.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies AG
    Inventor: Markus Dinkel
  • Shielded package assemblies with integrated capacitor
    Patent number: 9935058
    Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Array substrate and method of mounting integrated circuit using the same
    Patent number: 9917113
    Abstract: An array substrate including a display area and a non-display area surrounding the display area. The non-display area includes a pad portion including one or more first pads that each have a parallelogram shape.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: March 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Geun Lee
  • Methods of simultaneously forming bottom and top spacers on a vertical transistor device
    Patent number: 9882025
    Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure around a vertically oriented channel semiconductor structure above a bottom source/drain (S/D) region and below a top source/drain (S/D) region, the gate structure comprising a gate electrode and a gate insulation layer, a first portion of the gate insulation layer being positioned between the gate electrode and the vertically oriented channel semiconductor structure, removing second portion and third portions of the gate insulation layer while leaving at least some of the first portion in position to define a top spacer recess and a lower spacer recess and performing a common deposition process to simultaneously form a top spacer in the top spacer recess and a lower spacer in the lower spacer recess.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: John H. Zhang
  • Stacked package device and method for fabricating the same
    Patent number: 9881901
    Abstract: A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of first bonding pads, and the second substrate includes a plurality of second bonding pads. A three-dimensional (3D) printing is performed to form an encapsulating layer covering the first substrate and the second substrate and to form a plurality of bonding wires in the encapsulating layer. Each bonding wire includes a first portion connected to one of the plurality of first bonding pads. The disclosure also provides a stacked package device formed by such a method.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 30, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yu-Cheng Chiao, Tung-Yi Chan, Chen-Hsi Lin, Chia Hua Ho, Meng-Chang Chan, Hsin-Hung Chou
  • Semiconductor interconnect structure with double conductors
    Patent number: 9837350
    Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
  • TIM strain mitigation in electronic modules
    Patent number: 9837332
    Abstract: A heat spreading lid including a lid body and a wing portion having a thermal interface material disposed on the wing portion such that the wing portion flexibly moves with the thermal interface material independently from the lid body.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard McVicker, Sri M. Sri-Jayantha
  • Display module with white light
    Patent number: 9831459
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • Quantum dot (QD) polymer composites for on-chip light emitting diode (LED) applications
    Patent number: 9825205
    Abstract: Quantum dot polymer composites for on-chip light emitting diode applications are described. In an example, a composite for on-chip light emitting diode application includes a polymer matrix, a plurality of quantum dots dispersed in the polymer matrix, and a base dispersed in the polymer matrix.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 21, 2017
    Assignee: Pacific Light Technologies Corp.
    Inventors: Kari N. Haley, Benjamin Daniel Mangum, Weiwen Zhao, Nathan Evan Stott, Juanita N. Kurtin
  • Semiconductor package assembly with passive device
    Patent number: 9818727
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: November 14, 2017
    Assignee: MEDIATEK INC.
    Inventors: Che-Hung Kuo, Ying-Chih Chen, Che-Ya Chou
  • Electrically conductive element, power semiconductor device having an electrically conductive element and method of manufacturing a power semiconductor device
    Patent number: 9812376
    Abstract: An electrically conductive element includes an electrically conductive material and a plurality of inclusions of a phase change material. The phase change material has a phase transition temperature Tc between 150° C. and 400° C. The inclusions are separated from each other and are embedded in the electrically conductive material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Stefan Woehlert, Michael Nelhiebel, Siegfried Roehl
  • Reacted conductive gate electrodes and methods of making the same
    Patent number: 9812572
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Prevention of premature breakdown of interline porous dielectrics in an integrated circuit
    Patent number: 9812399
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 7, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
  • Semiconductor packaging structure and method
    Patent number: 9799631
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer
    Patent number: 9786607
    Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Sukwon Hong, William J. Taylor, Jr.
  • Thermal conductive silicone composition and semiconductor device
    Patent number: 9783723
    Abstract: Provided is a thermal conductive silicone composition having a superior thermal conductivity. The thermal conductive silicone composition contains: (A) an organopolysiloxane that exhibits a kinetic viscosity of 10 to 100,000 mm2/s at 25° C., and is represented by the following average composition formula (1) R1aSiO(4-a)/2??(1) wherein R1 represents a hydrogen atom or at least one group selected from a hydroxy group and a saturated or unsaturated monovalent hydrocarbon group having 1 to 18 carbon atoms, and a satisfies 1.8?a?2.2; and (B) a silver powder having a tap density of not lower than 3.0 g/cm3 and a specific surface area of not larger than 2.0 m2/g, such silver powder being in an amount of 300 to 11,000 parts by mass with respect to 100 parts by mass of the component (A).
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 10, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shota Akiba, Kenichi Tsuji, Kunihiro Yamada