Patents Examined by Hoa B. Trinh
  • Method and processing apparatus for performing pre-treatment to form copper wiring in recess formed in substrate
    Patent number: 10068798
    Abstract: There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a surface of the substrate that defines the recess, and forming a seed layer on the barrier layer. The method further includes at least one of etching the barrier layer and etching the seed layer. In the at least one of etching the barrier layer and etching the seed layer, the substrate is inclined with respect to an irradiation direction of ions while rotating the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 4, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroyuki Toshima, Tatsuo Hatano, Shinji Furukawa, Naoki Watanabe, Naoyuki Suzuki
  • Semiconductor package and method for forming the same
    Patent number: 10068822
    Abstract: A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region; subsequently, disposing at least one die structure onto the active region of the substrate respectively; and then injecting a molding compound flowed into the gap region, to mold the flow hindering supporter and the die structure with the molding compound.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Semiconductor device
    Patent number: 10068861
    Abstract: Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 4, 2018
    Assignee: ChipMOS Technologies Inc.
    Inventor: Kun-Shu Chuang
  • Electronic device
    Patent number: 10049999
    Abstract: A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one Through Silicon Via (TSV), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at least one TSV. The at least one active chip may be a memory chip and a non-memory chip in a vertically stacked (3D) configuration, connected through an electrical path that includes the TSV of the dummy chip. Embodiments may include multiple memory chips and dummy chips.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seijin Kim
  • Electronic module comprising fluid cooling channel and method of manufacturing the same
    Patent number: 10037972
    Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Martin Gruber, Wolfram Hable
  • Light-emitting element
    Patent number: 10002991
    Abstract: A light-emitting element, comprises a light-emitting stack comprising an active layer; a window layer on the light-emitting stack, wherein the window layer has a surface opposite to the light-emitting stack; and an insulative layer on the surface, wherein the surface comprises a cavity and the insulative layer substantially conformally covering the cavity, and wherein the insulative layer has a first refractive index equal to or smaller than 1.4.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 19, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Wen-Luh Liao, Chun-Yu Lin, Kun-De Lin
  • Vertical multi-batch magnetic annealing systems for reduced footprint manufacturing environments
    Patent number: 10003018
    Abstract: Embodiments are described for annealing systems and related methods to process microelectronic workpieces using vertical multi-batch perpendicular magnetic annealing systems that allow for a side-by-side configuration of multiple annealing systems to satisfy reduced footprint requirements.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 19, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Saito Makoto, Noel O'Shaughnessy, Toru Ishii, David Hurley
  • Packages with stacked dies and methods of forming the same
    Patent number: 9984999
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Dean Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Interconnect structures and methods of formation
    Patent number: 9984976
    Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: May 29, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yana Cheng, Yong Cao, Srinivas Guggilla, Sree Rangasai Kesapragada, Xianmin Tang, Deenesh Padhi
  • Manufacturing method of a flip-chip light emitting diode package module
    Patent number: 9978915
    Abstract: The instant disclosure relates to a flip-chip LED package module and a method of manufacturing thereof. The method of manufacturing flip-chip LED package module comprises the following steps. A plurality of LEDs is disposed on a carrier. A packaging process is forming a plurality of transparent lens corresponding to LEDs and binding each other by a wing portion. A separating process is proceeding to form a plurality of flip-chip LED structures without the carrier. A bonding process is proceeding to attach at least one flip-chip LED structure on the circuit board.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 22, 2018
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Ming-Kun Weng, Meng-Sung Chou
  • Display driver integrated circuit and method of manufacturing the same
    Patent number: 9960193
    Abstract: A display driver integrated circuit and a method of manufacturing the same are provided. The method of manufacturing a display driver integrated circuit (DDI) including a first area, a second area, and an overlapping area in which the first area and the second area overlap each other includes forming a first pattern in the first area using a first reticle; and forming a second pattern in the second area using a second reticle, and ends of the first pattern and the second pattern are connected within the overlapping area and the first area and the second area are asymmetrically set based on the overlapping area such that the overlapping area includes only a metal line.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Park, Siwoo Kim
  • Organic electroluminescent element
    Patent number: 9960363
    Abstract: The present invention provides an organic electroluminescent element which comprises: an anode; a cathode; and an organic layer interposed between the anode and the cathodes, wherein the organic layer comprises one or more types of layer from the group consisting of a hole-injection layer, hole-transport layer, light-emitting layer, lifetime enhancement layer, electron-transport layer, and electron-injection layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 1, 2018
    Assignee: DOOSAN CORPORATION
    Inventors: Min-Sik Eum, Ho-Cheol Park, Chang Jun Lee, Tae Hyung Kim, Jiyi Kim, Youngmi Beak
  • Process for fabricating semiconductor nanowires or microwires having insulated roots
    Patent number: 9954141
    Abstract: A process for fabricating an electronic device including a substrate and microwires or nanowires resting on the substrate, the process including successive steps of covering the wires with an insulating layer, covering the insulating layer with an opaque layer, depositing a first photoresist layer over the substrate between the wires, etching the first photoresist layer over a first thickness by photolithography, etching the first photoresist layer remaining after the preceding step over a second thickness by plasma etching, etching the portion of the opaque layer not covered by the first photoresist layer remaining after the preceding step, etching the portion of the insulating layer not covered by the opaque layer, removing the first photoresist layer remaining after the preceding step, and removing the opaque layer.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: April 24, 2018
    Assignees: Aledia, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Eric Pourquier, Philippe Gibert, Brigitte Martin
  • Chip package structure and manufacturing method thereof
    Patent number: 9947551
    Abstract: A chip package structure and the manufacturing method thereof are provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 17, 2018
    Assignees: NIKO SEMICONDUCTOR CO., LTD., SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Chih-Cheng Hsieh, Hsiu-Wen Hsu
  • Electronic device including a metal substrate and a semiconductor module embedded in a laminate
    Patent number: 9935027
    Abstract: An electronic device having a substrate including a metal layer, an electrically insulating layer disposed above the substrate, a semiconductor module disposed above the electrically insulating layer and a lamination layer disposed above the electrically insulating layer. The lamination layer at least partially embeds the semiconductor module.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies AG
    Inventor: Markus Dinkel
  • Wafer-level package with at least one input/output port connected to at least one management bus
    Patent number: 9934179
    Abstract: A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.
    Type: Grant
    Filed: February 14, 2016
    Date of Patent: April 3, 2018
    Assignee: MEDIATEK INC.
    Inventor: Yao-Chun Su
  • Shielded package assemblies with integrated capacitor
    Patent number: 9935058
    Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Array substrate and method of mounting integrated circuit using the same
    Patent number: 9917113
    Abstract: An array substrate including a display area and a non-display area surrounding the display area. The non-display area includes a pad portion including one or more first pads that each have a parallelogram shape.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: March 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Geun Lee
  • Methods of simultaneously forming bottom and top spacers on a vertical transistor device
    Patent number: 9882025
    Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure around a vertically oriented channel semiconductor structure above a bottom source/drain (S/D) region and below a top source/drain (S/D) region, the gate structure comprising a gate electrode and a gate insulation layer, a first portion of the gate insulation layer being positioned between the gate electrode and the vertically oriented channel semiconductor structure, removing second portion and third portions of the gate insulation layer while leaving at least some of the first portion in position to define a top spacer recess and a lower spacer recess and performing a common deposition process to simultaneously form a top spacer in the top spacer recess and a lower spacer in the lower spacer recess.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: John H. Zhang
  • Stacked package device and method for fabricating the same
    Patent number: 9881901
    Abstract: A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of first bonding pads, and the second substrate includes a plurality of second bonding pads. A three-dimensional (3D) printing is performed to form an encapsulating layer covering the first substrate and the second substrate and to form a plurality of bonding wires in the encapsulating layer. Each bonding wire includes a first portion connected to one of the plurality of first bonding pads. The disclosure also provides a stacked package device formed by such a method.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 30, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yu-Cheng Chiao, Tung-Yi Chan, Chen-Hsi Lin, Chia Hua Ho, Meng-Chang Chan, Hsin-Hung Chou