Abstract: An electronic assembly has a carrier substrate with contact surfaces and at least one electrical component on the carrier substrate. On its surface that is oriented toward the carrier substrate, the component has a number of contacting solder balls, which are respectively connected to a contact surface assigned to them. On the surface of the electrical component that is oriented toward the carrier substrate there is also arranged at least one fixing solder ball, which has a greater diameter than the contacting solder balls. The carrier substrate has at the location at which the at least one fixing solder ball is in contact with the carrier substrate a depression, in which the fixing solder ball is placed.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: A method includes forming a semiconductor device comprising a semiconductor die surrounded by a molding material, wherein a contact metal of the semiconductor device has an exposed edge, placing the semiconductor device into a tray having an inner wall and an outer wall, wherein the inner wall is underneath the semiconductor device and between an outer edge of the semiconductor device and an outer edge of bumps of the semiconductor device, depositing a metal shielding layer on the semiconductor device and the tray, wherein the metal shielding layer is in direct contact with the exposed edge of the contact metal and separating the semiconductor device from the tray.

Abstract: A light-emitting element includes a semiconductor stacked body, a light transmissive conductive film disposed on the semiconductor stacked body, the light transmissive conductive film including a plurality of through holes, insulation films disposed in the plurality of through holes, the plurality of through holes being disposed on the semiconductor stacked body; and a pad electrode disposed on the light transmissive conductive film and the insulation films.

Abstract: A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both the first logic die and the second logic die, a redistribution layer (RDL) structure coupled to the first logic die and the second logic die, and a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die. The first logic die and the second logic die are coplanar.

Abstract: Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.

Abstract: A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first P-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a third semiconductor region. The N-type well region and the P-type well region are disposed in the substrate. The first N-type semiconductor region is disposed in the N-type well region. The first P-type semiconductor region is disposed in the P-type well region. The second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The third semiconductor region is located between the second N-type semiconductor region and the second P-type semiconductor region.

Abstract: Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer.

Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.

Abstract: A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad.

Abstract: A semiconductor device is provided. The semiconductor device may include a frame portion on which at least one semiconductor chip is arranged; a plurality of leads electrically connected to the semiconductor chip; and a mold portion formed on the frame portion to surround a part of the frame portion on which the semiconductor chip and the plurality of leads are arranged, wherein a gap between closest portions of the respective leads is at least 2.9 mm.

Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.

Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.

Abstract: A method includes forming a molded panel that includes a number of integrated circuits, fan-out components and stiffeners embedded in an encapsulation material. A redistribution layer is formed over the integrated circuits and the fan-out components. The redistribution layer is electrically coupled to contacts of the integrated circuits. The molded panel is singulated to form electronic devices. Each electronic device each an integrated circuit that is separated from a fan-out component by a portion of the encapsulation material and a stiffener separated from the fan-out component by a second portion of the encapsulation material.

Abstract: A light-emitting device comprises a reflective layer; a first transparent layer on the reflective layer; a light-emitting stack comprising an active layer on the first transparent layer; and a cavity in the first transparent layer.

Abstract: A contact pad structure includes alternately stacked N insulating layers (N?6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions.

Abstract: The present disclosure relates to an aluminum electrode, a method of forming an aluminum electrode and an electronic device therewith. An aluminum electrode according to one aspect of the present disclosure comprises: a bottom layer consisting of molybdenum; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C. An aluminum electrode according to one embodiment of the present disclosure eliminates the mouse bite phenomenon. An aluminum electrode according to another aspect of the present disclosure comprises: a bottom layer consisting of a metal or metal-alloy nitride; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C.

Abstract: An optoelectronic element comprises a semiconductor stack comprising an active layer, wherein the semiconductor stack has a first surface and a second surface opposite to the first surface; a first transparent layer on the second surface; a plurality of cavities in the first transparent layer; and a layer on the first transparent layer, wherein the first transparent layer comprises oxide or diamond-like carbon.