Patents Examined by Hoa B. Trinh
  • Patent number: 9721933
    Abstract: A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9721923
    Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 1, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 9711435
    Abstract: A semiconductor device is provided. The semiconductor device may include a frame portion on which at least one semiconductor chip is arranged; a plurality of leads electrically connected to the semiconductor chip; and a mold portion formed on the frame portion to surround a part of the frame portion on which the semiconductor chip and the plurality of leads are arranged, wherein a gap between closest portions of the respective leads is at least 2.9 mm.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: July 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn-seung Lee, Jin-hyung Lee, Gil-yong Chang
  • Patent number: 9701534
    Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim
  • Patent number: 9698105
    Abstract: A method includes forming a molded panel that includes a number of integrated circuits, fan-out components and stiffeners embedded in an encapsulation material. A redistribution layer is formed over the integrated circuits and the fan-out components. The redistribution layer is electrically coupled to contacts of the integrated circuits. The molded panel is singulated to form electronic devices. Each electronic device each an integrated circuit that is separated from a fan-out component by a portion of the encapsulation material and a stiffener separated from the fan-out component by a second portion of the encapsulation material.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 4, 2017
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En Luan
  • Patent number: 9698368
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 4, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • Patent number: 9698116
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9691943
    Abstract: A light-emitting device comprises a reflective layer; a first transparent layer on the reflective layer; a light-emitting stack comprising an active layer on the first transparent layer; and a cavity in the first transparent layer.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: June 27, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Wen-Luh Liao
  • Patent number: 9685408
    Abstract: A contact pad structure includes alternately stacked N insulating layers (N?6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: June 20, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yu-Wei Jiang, Teng-Hao Yeh, Chia-Jung Chiou, Chih-Yao Lin
  • Patent number: 9685252
    Abstract: The present disclosure relates to an aluminum electrode, a method of forming an aluminum electrode and an electronic device therewith. An aluminum electrode according to one aspect of the present disclosure comprises: a bottom layer consisting of molybdenum; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C. An aluminum electrode according to one embodiment of the present disclosure eliminates the mouse bite phenomenon. An aluminum electrode according to another aspect of the present disclosure comprises: a bottom layer consisting of a metal or metal-alloy nitride; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 20, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Can Wang, Fang Liu, Yingwei Liu
  • Patent number: 9685588
    Abstract: An optoelectronic element comprises a semiconductor stack comprising an active layer, wherein the semiconductor stack has a first surface and a second surface opposite to the first surface; a first transparent layer on the second surface; a plurality of cavities in the first transparent layer; and a layer on the first transparent layer, wherein the first transparent layer comprises oxide or diamond-like carbon.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 20, 2017
    Assignee: Epistar Corporation
    Inventors: Wen-Luh Liao, Shao-Ping Lu, Hung-Ta Cheng, Shih-I Chen, Chia-Liang Hsu, Shou-Chin Wei, Ching-Pei Lin, Yu-Ren Peng, Chien-Fu Huang, Wei-Yu Chen, Chun-Hsien Chang
  • Patent number: 9679842
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 13, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Wei-Che Huang, Tzu-Hung Lin
  • Patent number: 9679859
    Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9679843
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Patent number: 9679810
    Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Shishir K. Ray, Andrew H. Simon, Oleg Gluschenkov, Siddarth A. Krishnan, Michael P. Chudzik
  • Patent number: 9673156
    Abstract: A package structure includes a first insulation layer, at least one first electronic component, and a first re-distribution layer. The first electronic component is embedded within the first insulation layer, and the first electronic component includes plural first conducting terminals disposed on a bottom surface of the first electronic component. At least part of the bottom surface of the first electronic component is exposed from a bottom surface of the first insulation layer. The first re-distribution layer is formed on the bottom surface of the first insulation layer and contacted with the corresponding first conducting terminals.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: June 6, 2017
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventors: Yiu-Wai Lai, Da-Jung Chen
  • Patent number: 9672323
    Abstract: A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, ??, varies in a substrate. The method focuses in on the difference in ?? with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in ?? with a smaller length scale (high frequency) and corrects only the difference in ?? with a greater length scale. The distribution of the difference in ?? in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in ?? with a low frequency and the difference in ?? between before and after correction, thereby revealing a part that requires correction.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sayuri Hada, Keiji Matsumoto
  • Patent number: 9673362
    Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: June 6, 2017
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventor: Naoyuki Urasaki
  • Patent number: 9673119
    Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
  • Patent number: 9666556
    Abstract: An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Liu, Chien-Kuo Chang, Chi-Yang Yu, Jing Ruei Lu, Chih-Hao Lin