Abstract: The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. The invention also includes methods of estimating the fractionation of a low concentration of one or more alpha particle emitters during purification of a material.

Abstract: A light-emitting element comprises a light-emitting stack comprising an active layer for emitting a light; a window layer on the light-emitting stack; and a first insulative layer having a first refractive index on the window layer; wherein the first insulative layer has a first refractive index, and the window layer has a second refractive index, and a difference between the first refractive index and the second refractive index is larger than 1.5.

Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.

Abstract: In a semiconductor device, a plurality of semiconductor units is electrically connected in parallel using a connecting device. The connecting device includes a first connecting unit and a second connecting unit. The first connecting unit is electrically connected to a control terminal of each semiconductor unit. The second connecting unit is electrically connected to a main terminal of each semiconductor unit.

Abstract: Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer.

Abstract: The invention relates to a light-emitting diode arrangement having the following: a preferably heat-conductive substrate (2); a printed circuit board (5) which is arranged on the substrate (2), a recess (9) being provided in the printed circuit board (5); and at least one light-emitting diode chip (3) which is arranged on the substrate (2) and in the recess (9), said recess (9) being at least partly filled with at least one matrix material which preferably has a color-converting material (8).

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract: A substrate is disclosed, which can remove heat from a stacked body of semiconductor elements through a phase change of a coolant. The substrate of the application includes: a stacked body of semiconductor elements; a first channel forming a path, receiving circulation of a first coolant, in a surface of the stacked body; and a second channel forming a path, receiving circulation of a second coolant having a boiling point higher than the boiling point of the first coolant, in an inter-layer portion of the stacked body.

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence having an active layer that generates radiation and at least one n-doped layer adjoining the active layer, the semiconductor layer sequence is based on AlInGaN or on InGaN, one or a plurality of central layers composed of AlGaN each having thicknesses of 25 nm to 200 nm are grown at a side of the n-doped layer facing away from a carrier substrate, a coalescence layer of doped or undoped GaN having a thickness of 300 nm to 1.2 ?m is formed at a side of the central layer or one of the central layers facing away from the carrier substrate, a roughening extends from the coalescence layer as far as or into the n-doped layer, a radiation exit area of the semiconductor layer stack is formed partly by the coalescence layer, and the central layer is exposed in places.

Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound, the die attach area having exposed areas to facilitate device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads; connection traces electrically couple the I/O terminals with one another, said connection traces having facilitated electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. An envelope of molding compound encapsulates the device die onto the built-up substrate lead frame.

Abstract: The present disclosure relates to an aluminum electrode, a method of forming an aluminum electrode and an electronic device therewith. An aluminum electrode according to one aspect of the present disclosure comprises: a bottom layer consisting of molybdenum; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C. An aluminum electrode according to one embodiment of the present disclosure eliminates the mouse bite phenomenon. An aluminum electrode according to another aspect of the present disclosure comprises: a bottom layer consisting of a metal or metal-alloy nitride; a top layer consisting of molybdenum; and an aluminum layer located between the bottom layer and the top layer, wherein the bottom layer, the top layer and the aluminum layer are formed at a temperature below 120° C.

Abstract: A wiring substrate includes a connection pad formed in the outermost wiring layer, a dummy pad formed in the outermost wiring layer, and a dummy wiring portion formed in the outermost wiring layer, the dummy wiring portion connecting the connection pad and the dummy pad. The maximum width of each of the connection pad and the dummy pad is set to be larger than the width of the dummy wiring portion. A bump of an electronic component is flip-chip connected to a connection pad through a resin-containing solder.

Abstract: A wiring substrate includes a first wiring substrate, a first insulation layer stacked on the first wiring layer, and second and third insulation layers sequentially stacked on the first insulation layer. An electronic component is mounted on the first insulation layer in a cavity extending through the second and third insulation layers. The cavity is filled with a fourth insulation layer that entirely covers an upper surface of the third insulation layer and covers the electronic component. A second wiring layer is incorporated in the second and third insulation layers and electrically connected to the first wiring layer. The second wiring layer is electrically connected to a third wiring layer, which is stacked on the fourth insulation layer, by a first via wiring extending through the second and third insulation layers.

Abstract: Light emitting semiconductor junctions are disclosed. An exemplary light emitting junction has a first electrical contact coupled to a first side of the junction. The exemplary junction also has a second electrical contact coupled to a second side of the junction. The exemplary junction also has a region of set straining material that exerts a strain on the junction and alters both: (i) an optical polarization, and (ii) an emission wavelength of the junction. The region of set straining material is not on a current path between said first electrical contact and said second electrical contact. The region of set straining material covers a third side and a fourth side of the light emitting junction along a cross section of the light emitting junction. The light emitting semiconductor junction device comprises a three-five alloy.

Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.

Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).

Abstract: Optoelectronic modules for light emitting and/or light sensing include optical assemblies and active optoelectronic components. An optical assembly and a corresponding optoelectronic component can be aligned. The optoelectronic modules can include multiple optical assemblies and active optoelectronic components. Multiple optical assemblies and corresponding active optoelectronic components can be aligned independently of each other in various implementations of optoelectronic modules that include alignment features and optical assembly barrels.

Abstract: Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip.

Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip, a groove formed in a periphery of a surface of the semiconductor chip being tapered toward a rear surface of the semiconductor chip, wherein the sealing resin layer is partly disposed in the groove.

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.