Abstract: A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode and made of a copper film, a solder ball electrode formed on the post electrode and made of ternary alloy containing tin, a terminal connected to the solder ball electrode and formed on a front surface of a wiring board, and a sealing material filling a gap between the semiconductor substrate and the wiring board. The post electrode includes a cylindrical stem portion and an overhanging portion positioned in an upper part of the stem portion and protruding to an outer side of the stem portion, the solder ball electrode is connected to an upper surface of the post electrode over the stem portion and the overhanging portion, and a sidewall of the stem portion contacts with the sealing material over the entire circumference thereof.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

Abstract: An object is to provide a method for manufacturing a wavelength selective heat radiation material in which a surface roughness of an upper portion of a cavity wall defining each microcavity is suppressed or in which microcavities each having an aspect ratio larger than 3.0 are formed. For the wavelength selective heat radiation material, a base material having a mask having predetermined openings tightly adhered to a surface thereof, or a base material in which depressions are previously formed on one surface thereof by pressing a die having projections arrayed so as to correspond to positions of microcavities thereagainst, is subjected to anisotropic etching, thereby providing a wavelength selective heat radiation material in which the surface roughness of the upper portion of the cavity wall defining each of the microcavities is suppressed or a wavelength selective heat radiation material having microcavities whose each aspect ratio is larger than 3.0.

Abstract: A method for manufacturing a semiconductor device includes forming an insulating layer on a semiconductor layer; forming a metal layer on the insulating layer; and forming a first interconnect by selectively etching the metal layer. The first interconnect is electrically connected to the semiconductor layer and has a loop configuration. The method includes forming a first mask layer covering the first interconnect and the insulating layer; and forming a second mask layer on the first mask layer. The second mask layer has a first opening over a portion of the first interconnect. The method further includes exposing the portion of the first interconnect by selectively removing the first mask layer using the second mask layer; and forming a second interconnect by selectively removing the portion of the first interconnect using the first mask layer. The second interconnect has two ends and is electrically connected to the semiconductor layer.

Abstract: A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad.

Abstract: A contact pad structure includes alternately stacked N insulating layers (N?6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions.

Abstract: A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.

Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.

Abstract: An LED packaging includes a substrate having a top surface and a bottom surface opposite to the top surface, a recess defined in the top surface, an LED mounted on the top surface of the substrate, a zener diode received in the recess, and a reflecting layer formed in the recess and enclosing the zener diode therein.

Abstract: The instant disclosure relates to a flip-chip LED package module and a method of manufacturing thereof. The method of manufacturing flip-chip LED package module comprises the following steps. A plurality of LEDs is disposed on a carrier. A packaging process is forming a plurality of transparent lens corresponding to LEDs and binding each other by a wing portion. A separating process is proceeding to form a plurality of flip-chip LED structures without the carrier. A bonding process is proceeding to attach at least one flip-chip LED structure on the circuit board.

Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract: An electronic device may include an integrated circuit (IC), electrically conductive connectors coupled to the IC, and a heat sink layer adjacent the IC and opposite the electrically conductive connectors. The electronic device may include an encapsulation material surrounding the IC and the electrically conductive connectors, a redistribution layer having electrically conductive traces coupled to the electrically conductive connectors, a stiffener between the heat sink layer and the redistribution layer, and a fan-out component between the heat sink layer and the redistribution layer and being in the encapsulation material.

Abstract: An electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and said encapsulating structure.

Abstract: Disclosed are a light-emitting diode package and a method for manufacturing same. The method for manufacturing a light-emitting diode package comprises: preparing a package main body having a cavity and an air vent passageway which extends from the cavity; installing a light-emitting diode inside the cavity of the package main body; attaching a transparent member by means of an adhesive so as to cover the upper part of the cavity; and blocking the air vent passageway by forming a sealing member. As the air vent passageway is blocked after the transparent member is attached, the transparent member may be prevented from peeling off from the air pressure inside the cavity.

Abstract: A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies electrically connected in series, in parallel, or in any combination of series and parallel, to provide such a SMD having one or more different functions including wave filtration, rectification, surge protection, sensing, current limiting, voltage regulation or prevention from voltage backflow, as compared to the prior art, the SMD disclosed is formed from fewer components, is simpler to manufacture and more effectively reduce layout wire length and noise.

Abstract: A lid including a lid body, and a wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible independent from a portion of the lid body adjacent to the edge of the wing portion.

Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.