Patents Examined by Hoa B. Trinh
  • Method of connecting a semiconductor package to a board
    Patent number: 9343397
    Abstract: A method of connecting a semiconductor package to a board includes providing a board having a plurality of contact regions, providing a semiconductor package having a plurality of contact areas, selecting a specific contact area out of the plurality of contact areas, applying solder balls to the contact areas and therein applying two or more specific solder balls to the specific contact area, and connecting the semiconductor package to the board in such a way that the two or more specific solder balls are connected with each other and with a contact region of the plurality of contact regions of the board.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 17, 2016
    Assignee: Infineon Technologies AG
    Inventor: Carlo Marbella
  • Laser marking in packages
    Patent number: 9343434
    Abstract: A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Reacted conductive gate electrodes and methods of making the same
    Patent number: 9343539
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Packages with stacked dies and methods of forming the same
    Patent number: 9343433
    Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Tsung-Ding Wang, Mirng-Ji Lii, Chen-Hua Yu
  • Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip
    Patent number: 9343615
    Abstract: A method of producing an optoelectronic semiconductor chip includes providing a growth substrate, producing a III nitride nucleation layer on the growth substrate by sputtering, wherein a material of the growth substrate differs from a material of the nucleation layer, and growing a III nitride semiconductor layer sequence having an active layer onto the nucleation layer.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 17, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Joachim Hertkorn, Karl Engl, Berthold Hahn, Andreas Weimar
  • Semiconductor device and related manufacturing method
    Patent number: 9343435
    Abstract: A method for manufacturing a semiconductor device may include providing a first dielectric layer and a first set of conductive pads on a first substrate. Each conductive pad of the first set of conductive pads may be positioned between portions of the first dielectric layer. The method may further include providing a first insulating material layer to cover the first dielectric layer and the first set of conductive pads. The method may further include removing portions of the first insulating material layer to form a first insulating layer. Openings of the first insulating layer may expose the first set of conductive pads.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 17, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Fucheng Chen, Yao Liu, Herb He Huang
  • Hermetic wafer level packaging
    Patent number: 9337168
    Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
  • Integrated circuit package with voltage distributor
    Patent number: 9331046
    Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chu-Chung Lee, Kian Leong Chin, Kevin J. Hess, James Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
  • Light-emitting element having a reflective structure with high efficiency
    Patent number: 9331247
    Abstract: A light-emitting element includes a reflective layer; a first transparent layer on the reflective layer; a light-emitting stack having an active layer on the first transparent layer; and a cavity formed in the first transparent layer.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 3, 2016
    Assignee: Epistar Corporation
    Inventors: Wen-Luh Liao, Shao-Ping Lu, Hung-Ta Chen, Shih-I Chen, Chia-Liang Hsu, Shou-Chin Wei, Ching-Pei Lin, Yu-Ren Peng, Chien-Fu Huang, Wei-Yu Chen, Chun-Hsien Chang
  • Light-emitting element
    Patent number: 9318663
    Abstract: A light-emitting element comprises a light-emitting stack comprising an active layer, a first insulative layer having a first refractive index on the light-emitting stack, a second insulative layer having a second refractive index on the first insulative layer, and a transparent conducting structure having a third refractive index on the second insulative layer, wherein the second refractive index is between the first refractive index and the third refractive index, and the first refractive index is smaller than 1.4.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 19, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Ching-Yuan Tsai, Hsin-Chan Chung, Wen-Luh Liao
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 9312228
    Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: April 12, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Semiconductor device and method for making same
    Patent number: 9312172
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Integrated circuit package and method of making same
    Patent number: 9299661
    Abstract: An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side. The package also includes a die having an active surface affixed to a contact location of the first side of the dielectric film. A die stud is affixed to the active surface of the die and extends through the dielectric film to an interconnect location of the second side of the dielectric film.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: March 29, 2016
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, James Sabatini
  • Method for manufacturing a semiconductor device, and semiconductor device
    Patent number: 9293409
    Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 22, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Fischer, Carsten Ahrens, Damian Sojka, Andre Schmenn
  • Headset connector
    Patent number: 9287657
    Abstract: Headset assemblies and headset connectors are provided. Headset connectors can include a magnetic mating face and a plurality of electrical contacts disposed within the mating face. Engaging assemblies and engaging connectors are also provided. The engaging connectors can include a housing having a mating side, a magnetic array structure, and a plurality of spring biased contact members. The magnetic array structure can be fixed within the housing and house a plurality of spring biased contact members. The spring biased contact members can include tips that extend out of the mating side. The tips can electrically couple with electrical contacts in a headset connector.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: March 15, 2016
    Assignee: Apple Inc.
    Inventors: M. Evans Hankey, Emery A. Sanford, Christopher D. Prest, Way Chet Lim
  • High power ceramic on copper package
    Patent number: 9269594
    Abstract: According to an embodiment of a high power package, the package includes a heat sink containing enough copper to have a thermal conductivity of at least 350 W/mK, an electrically insulating attached to the heat sink with an epoxy and a semiconductor chip attached to the heat sink on the same side as the lead frame with an electrically conductive material having a melting point of 280° C. or greater.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Anwar Mohammed, Julius Chew, Donald Fowlkes
  • Independent control of stacked electronic modules
    Patent number: 9269403
    Abstract: Various embodiments of apparatuses are disclosed to allow independent control of stacked modules. In one embodiment, an apparatus may include a plurality of stacked memory dice, with at least some of the plurality of stacked memory dice include a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the dice. Each of the stacked dice having the CE signal connection is controllable individually by a unique CE signal applied to the CE signal connection. Other apparatuses are disclosed.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Robert N Schenck, Steven R. Eskildsen
  • Localized high density substrate routing
    Patent number: 9269701
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Semiconductor device and method for making same
    Patent number: 9263328
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Semiconductor device having multiple chips mounted to a carrier
    Patent number: 9263421
    Abstract: A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first semiconductor chip mounted on the first surface of the chip carrier. A second semiconductor chip is mounted on the second surface of the chip carrier, wherein a portion of a first surface of the second semiconductor chip which faces the chip carrier projects over an edge of the chip carrier. A first electrical conductor is coupled to an electrode formed on the portion of the first surface of the second semiconductor chip that projects over the edge of the chip carrier.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Boon Seong Lee, Chee Voon Tan