Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.
Abstract: An LED packaging includes a substrate having a top surface and a bottom surface opposite to the top surface, a recess defined in the top surface, an LED mounted on the top surface of the substrate, a zener diode received in the recess, and a reflecting layer formed in the recess and enclosing the zener diode therein.
Type:
Grant
Filed:
June 20, 2014
Date of Patent:
November 15, 2016
Assignee:
ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
Abstract: The instant disclosure relates to a flip-chip LED package module and a method of manufacturing thereof. The method of manufacturing flip-chip LED package module comprises the following steps. A plurality of LEDs is disposed on a carrier. A packaging process is forming a plurality of transparent lens corresponding to LEDs and binding each other by a wing portion. A separating process is proceeding to form a plurality of flip-chip LED structures without the carrier. A bonding process is proceeding to attach at least one flip-chip LED structure on the circuit board.
Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
Type:
Grant
Filed:
October 30, 2015
Date of Patent:
October 25, 2016
Assignee:
Fairchild Semiconductor Corporation
Inventors:
Ahmad R. Ashrafzadeh, Vijay G. Ullal, Justin Chiang, Daniel Kinzer, Michael M. Dube, Oseob Jeon, Chung-Lin Wu, Maria Cristina Estacio
Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.
Type:
Grant
Filed:
January 11, 2016
Date of Patent:
October 18, 2016
Assignee:
SAMSUNG ELECTRONICS CO., LTD.
Inventors:
Yong-Hoon Kim, Hyo-Soon Kang, Hee-Seok Lee, Jang-Ho Cho
Abstract: An electronic device may include an integrated circuit (IC), electrically conductive connectors coupled to the IC, and a heat sink layer adjacent the IC and opposite the electrically conductive connectors. The electronic device may include an encapsulation material surrounding the IC and the electrically conductive connectors, a redistribution layer having electrically conductive traces coupled to the electrically conductive connectors, a stiffener between the heat sink layer and the redistribution layer, and a fan-out component between the heat sink layer and the redistribution layer and being in the encapsulation material.
Abstract: An electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and said encapsulating structure.
Type:
Grant
Filed:
March 16, 2012
Date of Patent:
October 4, 2016
Assignee:
FLEXENABLE LIMITED
Inventors:
Daniel Garden, Jan Jongman, Martin Lewis
Abstract: Disclosed are a light-emitting diode package and a method for manufacturing same. The method for manufacturing a light-emitting diode package comprises: preparing a package main body having a cavity and an air vent passageway which extends from the cavity; installing a light-emitting diode inside the cavity of the package main body; attaching a transparent member by means of an adhesive so as to cover the upper part of the cavity; and blocking the air vent passageway by forming a sealing member. As the air vent passageway is blocked after the transparent member is attached, the transparent member may be prevented from peeling off from the air pressure inside the cavity.
Type:
Grant
Filed:
October 9, 2012
Date of Patent:
September 20, 2016
Assignee:
Seoul Viosys Co., Ltd.
Inventors:
Hee Cheul Jung, Jung Hye Chae, Bo Ram I Jang, Jun Yong Park, Dae Woong Suh
Abstract: A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies electrically connected in series, in parallel, or in any combination of series and parallel, to provide such a SMD having one or more different functions including wave filtration, rectification, surge protection, sensing, current limiting, voltage regulation or prevention from voltage backflow, as compared to the prior art, the SMD disclosed is formed from fewer components, is simpler to manufacture and more effectively reduce layout wire length and noise.
Abstract: A lid including a lid body, and a wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible independent from a portion of the lid body adjacent to the edge of the wing portion.
Type:
Grant
Filed:
February 25, 2014
Date of Patent:
September 6, 2016
Assignee:
International Business Machines Corporation
Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
Type:
Grant
Filed:
February 26, 2014
Date of Patent:
August 23, 2016
Assignee:
Taiwan Semiconductor Manufacturing Company Limited
Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.
Abstract: A lighting apparatus includes a substrate, a plurality of light-emitting dies disposed on the substrate and spaced apart from one another, a continuous structure disposed over the substrate and covering the light-emitting dies within, and a filler. The light-emitting dies each are covered with an individual phosphor coating and the filler is between the continuous structure and the phosphor coating for each of the light-emitting dies. The lighting apparatus has a substantially white appearance when the plurality of light-emitting dies is turned off.
Abstract: A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package.
Type:
Grant
Filed:
August 11, 2014
Date of Patent:
August 9, 2016
Assignee:
Amkor Technology, Inc.
Inventors:
Ji Young Chung, Choon Heung Lee, Glenn Rinne, Byong Jin Kim
Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
Abstract: A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer.
Type:
Grant
Filed:
December 6, 2013
Date of Patent:
August 9, 2016
Assignee:
J-DEVICES CORPORATION
Inventors:
Yoshiyuki Tomonaga, Mitsuru Ooida, Katsumi Watanabe, Hidenari Sato
Abstract: Light emitting semiconductor junctions are disclosed. An exemplary light emitting junction has a first electrical contact coupled to a first side of the junction. The exemplary junction also has a second electrical contact coupled to a second side of the junction. The exemplary junction also has a region of set straining material that exerts a strain on the junction and alters both: (i) an optical polarization, and (ii) an emission wavelength of the junction. The region of set straining material is not on a current path between said first electrical contact and said second electrical contact. The region of set straining material covers a third side and a fourth side of the light emitting junction along a cross section of the light emitting junction. The light emitting semiconductor junction device comprises a three-five alloy.
Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.
Abstract: In a laser welding method, a gap between first and second members to be welded is made at most 300 ?m by pressing the second member against the first member with claws that are pressing parts of a laser welding jig, and the second member to be welded at a place between the claws is irradiated by laser light to laser-weld the first member and the second member. In a semiconductor device, the gap between the first member and the second member at the portion of laser-welding is at most 300 ?m.