Abstract: A probe for a circuit board tester as well as to an adapter and a circuit board tester. The probe comprises a needle and a sleeve, the needle being shiftingly guided in the sleeve and the needle protruding at least 10 mm from the sleeve, more particularly more than 20 mm. In one embodiment, the needle is conically tapered to a contact tip at least in a portion protruding from the sleeve. With the probe in accordance with the invention, adapters for circuit boards can be produced comprising contacts in high-density, the probes simultaneously acting resiliently.

Abstract: Two connector printed circuit boards with electrical connections are mounted on opposite sides of a mid-plane printed circuit board at angles to each other. Via holes are positioned on the faces of the mid-plane board according to one of two schemes. In the first scheme, the via holes are positioned along an axis perpendicular to an axis that bisects the angle of misalignment of the connector boards, and the via holes are equidistant from a point on the axis that bisects the angle of misalignment of the connector boards. In the second scheme, the via holes are positioned along an axis that bisects the angle of misalignment of the connector boards, and the via holes are equidistant from the electrical connections.

Abstract: To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone.

Abstract: A coaxial via hole structure used in a carrier is disclosed. The coaxial via hole includes an outer cylinder-shaped conductor, an inner cylinder-shaped conductor and an intermediate fill. The outer cylinder-shaped conductor extends along a first direction. The inner cylinder-shaped conductor is disposed in the outer cylinder-shaped conductor and also extends along the first direction. The intermediate fill is between the outer cylinder-shaped conductor and the inner cylinder-shaped conductor and is made of insulating material or electrical-resistant material. The coaxial via hole structure can be applied as a capacitor or a resistor and has the function of signal shielding.

Abstract: Integrated packages incorporating multilayer ceramic circuit boards mounted on a metal support substrate can be used for temperature control by the metal support substrate. Various electronic components, as well as additional temperature control devices, can be connected to the circuit boards and to the metal support substrate to control or regulate the temperature of operation of the components. The integrated package can be hermetically sealed with a lid.

Abstract: A flip chip package substrate is disclosed. The substrate is correspondingly flip chip bonded to a first chip, a second chip, and so on, wherein these chips are of similar type of pad arrangement but of different pad pitches. The top face of the flip chip package substrate is provided with a plurality of bump pad groups, and these bump pad groups are respectively provided with a plurality of bump pads in the sequence of a first bump pad, a second bump pad, and so on, and a plurality of bump pads of the same bump pad group are electrically connected with each other, and the positions of the first bump pads are respectively corresponding to the positions of the second pads, and the rest may be inferred by analogy. Hence, these chips share the same flip chip package substrate.

Abstract: In a wiring board having a terminal for connection of circuits in a variety of electronic devices, a joining section of the terminal is placed on a connecting section of a wiring pattern on the top surface of a lower substrate, two layers of adhesives having different softening temperatures are formed between the lower substrate and an upper substrate, and the lower substrate and the upper substrate are cemented sandwiching the joining section. With this structure, a stable holding force can be secured over a wide temperature range.

Abstract: A printed circuit board unit has smaller number of pins in connectors for connection of wiring (signal lines and power source lines) between a plurality of printed circuit boards for increasing mounting space of the board and interconnection method of wiring between printed circuit boards. The printed circuit board unit includes a plurality of printed circuit boards having wiring formed thereon, a part of the wiring on the printed circuit boards electrically connected through connectors, a screw formed of electrically conductive body and fixing the plurality of printed circuit boards with preventing the connectors from disengaging from each other, and remaining part of the wiring on the printed circuit boards electrically connected through the screw.

Abstract: In some embodiments, the invention includes a module including a circuit board and first and second groups of conductors supported by the circuit board. A first group of chips each include on die terminations that are enabled. At least some of a second group of chips have on die terminations that are disabled. The first group of chips are coupled to conductors of the first group of conductors and the second group of chips are coupled to conductors of the second group of conductors, and wherein the second group of conductors have higher impedances than do the first group of conductors.

Abstract: A flexible printed circuit board, supports electronics components, wiring, mechanical and components of an electromechanical transducer also acts as a main structural member for the entire microsystem.

Abstract: A switching device and a method for the configuration thereof is disclosed. A first aspect of the present invention comprises a switching device. The switching device comprises at least one line card and at least one switching card. The device includes a mid-plane coupled to the at least one line card and the at least one switching card. The A second aspect of the invention comprises a method for configuring a switching device. The method for configuring a switching device comprises providing a mid-plane, and providing at least one switching card and at least one line card on the mid-plane. The at least one switching card and the at least one line card are perpendicular to each other.

Abstract: A multi-layer wiring board comprises an insulating substrate having, on a central part of its top surface, a semiconductor device mounting portion and having, on its under surface, an external electrode. The insulating substrate includes a multilayered wiring having a first group of parallel wiring lines; a second group of parallel wiring lines arranged orthogonal thereto; and a group of through conductors for providing electrical connection therebetween. Power is supplied from the external electrode to the semiconductor device through built-in capacitors formed therewithin. The built-in capacitors are connected in parallel that have different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is equal to or below a predetermined value.

Abstract: A chip package structure comprising a chip and a substrate is provided. The chip has an active surface, a plurality of chip pads and a plurality of bonding columns. The chip pads are formed on the active surface, and the bonding columns are bonded to their respective chip pads. The substrate has a substrate surface, a solder mask layer, a plurality of junction pads and a plurality of trace lines. The substrate surface is divided into a chip junction region and a non-chip junction region. The junction pads and a portion of the trace lines are formed within the chip junction region on the substrate surface while the remaining trace lines are formed within the non-chip junction region on the substrate surface. The end of each bonding column is bonded to a corresponding junction pad. The chip package structure may further include an underfill layer that completely fills the space within the chip, the bonding columns and the substrate.

Abstract: A first package for an integrated circuit has both a first set of electrical contacts and a first connector. A second package has a second set of electrical contacts and a second connector. The first and the second connector are mating connectors that are electrically and physically coupled. The first set of electrical contacts and the first connector are disposed on opposite surfaces of the first package and the second set of electrical contacts and the second connector are disposed on the same surface of the second package. The first and second set of electrical contacts couple to a printed circuit board directly or indirectly through a socket. The connectors allow higher speed signals to be routed over the first and second connectors, while power, ground and slower speed signals can be routed over the first set and second set of electrical contacts.

Abstract: In the surface mount typed electronic circuit of the invention, an insulating substrate has an inductance element formed in a conductive pattern whose end portions are connected to the second lands. A bare chip is superimposed on the insulating substrate, so as to respectively connect the first electrodes and the second electrodes to the first lands and the second lands. Therefore, since the inductance element is positioned below the bare chip, the length of the connecting conductor between the inductance element and the semiconductor circuit can be extremely shortened, and a high-Q electronic circuit, especially in high-frequency, can be provided.

Abstract: A plurality of semiconductor chips bent along the outer circumferential surface of a cylindrical substrate are mounted to the outer circumferential surface of the substrate. The bumps of these semiconductor chips are connected to connection pads formed on the outer circumferential surface of the substrate. By diminishing the curvature radius of the bent semiconductor chips, the size of the semiconductor module can be made smaller than the size of the chip.

Abstract: A semiconductor device comprising integrated circuit elements realized by means of a stack of layers of semiconductor materials provided on a substrate of semiconductor material and comprising means for preventing the pollution of the circuit elements and of the substrate by hydrogen originating from their environment is characterized in that said means are formed by a layer of a material which absorbs hydrogen (or hydrogen getter) (10), which forms a pattern which is integrated with the circuit elements and whose outer surface (11) is exposed and in contact with the environment. This device, of the MMIC type, forms part of a module of a spatial or terrestrial telecommunication system.

Abstract: An electronic device having stacked modules and method for producing it are described. Each module has a chip. Each chip is mounted on a stack intermediate plane. The stack intermediate planes of a stack have identical layouts, while chip select circuits which can be set irreversibly via contact areas are disposed on the chips, which chip select circuits enable an irreversible assignment of the contact areas to the stack intermediate planes.

Abstract: The present invention has an object to provide a more compact semiconductor device that can be assembled with reduced parts and tasks. The semiconductor device includes a housing having a top and bottom surfaces. Surrounded within the housing is an insulating substrate with metal layers formed on both sides thereof. Also a semiconductor chip is mounted on one of the metal layer of the insulating substrate. A terminal connector extends along the top surface of the housing and is bent towards the bottom surface thereof for supplying power to the semiconductor chip. The housing has a housing through-hole extending from the top surface to the bottom surface through the housing, and the terminal connector has a terminal through-hole which are aligned with and formed coaxially with the housing through-hole.

Abstract: The invention relates to a conductor track layer structure precursor stage with conductor tracks, which are disposed on an electrically insulating substrate with an inner region and a lateral peripheral region and which are connected via conductor track current lines to at least one current line which extends in the lateral peripheral region. Per conductor track, there is one conductor track current line. The conductor tracks are electrically insulated from one another within the inner region of the conductor track layer structure precursor stage. The invention also relates to a conductor track layer structure which can be obtained from the conductor track layer structure precursor stage.