Abstract: A support circuit is adapted to be mechanically and electrically coupled to a semiconductor chip such that the support circuit and the chip in combination form a semiconductor chip assembly. The support circuit includes an insulative base and a conductive trace embedded in the insulative base. The conductive trace is a single continuous piece of metal, the conductive trace includes a pillar that extends above the insulative base and a routing line that is substantially covered by and extends below the insulative base, and an opening in the routing line has tapered sidewalls and a diameter that increases as height increases.

Abstract: The present invention provides an electronic device manufacturing method and an electronic device which make it possible to reduce the waste of materials and the number of manufacturing steps required. Electronic devices are manufactured via a process including creating a collective substrate, in which a plurality of substrates corresponding to the electronic devices being manufactured are connected in the form of a matrix, mounting electronic parts on the upper surface of the collective substrate, forming a solidified resin layer using a vacuum printing method so that said resin layer covers the upper surface of the collective substrate on which the aforementioned parts have been mounted, or an intermediate layer consisting of an insulating elastic material, and so that said resin layer covers the electronic parts, and separating the collective substrate on which the above-mentioned resin layer has been formed into individual substrates.

Abstract: The invention relates to a circuit substrate assembly comprising a left-hand (1) and a right-hand (1′) circuit substrate mirror-symmetrical thereto, each including electrical and/or electronic and/or electromechanical components (2-6 or 2′-6′) and circuitry (7 or 7′) electrical connecting said components. All components (2-6) are positioned symmetrically mirrored on the left-hand (1) and right-hand (1′) circuit substrate respectively when the left-hand (1) and right-hand (1′) circuit substrate is oriented mirror-symmetrical along a mirror plane (P). However, the circuit functional plug assignments (A-F) of at least one circuit functional mirror-invariant component 2 or 2′) on the left-hand (1) and on the right-hand (1′) circuit substrate are not mirror-symmetrical to each other.

Abstract: A circuit component built-in module of the present invention includes an insulating substrate formed of a mixture comprising 70 wt % to 95 wt % of an inorganic filler and a thermosetting resin, a plurality of wiring patterns formed on at least a principal plane of the insulating substrate, a circuit component arranged in an internal portion of the insulating substrate and electrically connected to the wiring patterns, and an inner via formed in the insulating substrate for electrically connecting the plurality of wiring patterns. Thus, a highly reliable circuit component built-in module having high-density circuit components can be obtained.

Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Abstract: A multi-level package, and method for making same, that offers a small size with compartmentalized areas that allow for radiation shielding is disclosed. In its simplest embodiment, the invention comprises two cards and an interposer interposed between the two cards. The interposer preferably has an opening, and the combination of the interposer's opening and the two cards form a cavity. The cavity allows for a high amount of components to be packed into a small, three-dimensional space. The interposer supports can act like a Faraday shield. The two cards and interposer can be multi-layered and support any type of chip or package connection on each side of each card or interposer, including through-hole, surface mount, and direct-chip attachment connections. Finally, pick-up plates or heat sinks can be attached to the package.

Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

Abstract: In a circuit board having a multilayer structure comprising a ground pattern and a power-supply pattern both, for example, by forming a plurality of slits along each side of the ground pattern or the power-supply pattern, a long thin conduction path connecting a corner and a side center of the ground pattern is formed and resistive elements are placed in the middles of the conduction path to short, circuit the corner and a side center of the ground pattern. Therefore, portions corresponding to an antinode and a node or antinode and an antinode of a standing wave are short-circuited. The standing wave is generated when electric power is supplied to ICs and LSIs mounted on the circuit board. Thus, noise sources caused by the standing wave cancel each other. As a result, the occurrence of an antiresonance phenomenon and an increase in impedance of the power supplying system caused by the standing wave can be suppressed.

Abstract: In a Compact PCI system, a method and apparatus for bridging multiple PCI segments in a chassis utilizing backplane connections, instead of a front side component slot. Embodiments of the present invention may be used, with either a transparent or non-transparent bridging system, between multiple PCI segments, to increase the number of shared peripherals in a single Compact PCI chassis.

Abstract: The invention provides an electronic circuit unit that is suitable for miniaturization and excellent in high frequency characteristic. Capacitors and a wiring pattern are formed on an alumina substrate by means of thin film forming technique, and a part of the wiring pattern is served as the connection land for mounting a bare chip of a transistor. Among the capacitors, the top electrode of the capacitor is served also as a part of the connection land, and the bottom side collector electrode of the bare chip is connected to the connection land by use of conductive adhesive. Top electrodes of the residual capacitors are served as the bonding pad, and the base electrode and the emitter electrode on the top side of the bare chip are connected to the top electrodes of the respective capacitors by a wire.

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, a pair of CSPs is stacked, with one CSP above the other. The two CSPs are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.

Abstract: A printed wiring board reduced in weight by reducing the size and the thickness of a substrate in its entirety. The printed wiring board includes a rigid substrate 2, comprised of a core material 11 at least one side of which carries a land 23, and flexible substrates 3, 4, 5 and 6 comprised of core materials 33, 36 on at least one surface of which a bump 32 for electrical connection to the land 38 is formed protuberantly. The rigid substrate 2 and the flexible substrates 3 to 6 are molded as one with each other, with the interposition of an adhesive in-between, so that the land and the bump face each other.

Abstract: An adapter or housing for a module, such as a single in-line memory module (SIMM) or the like, and method of using the same are herein disclosed where the SIMM and attached housing fit a predetermined-shape SIMM socket. The housing replaces SIMM board material that would otherwise be used to help secure the SIMM to a predetermined-shape SIMM socket or connector. The configuration of the housing allows a SIMM or the like to be snapped or slid and secured into the housing. If desired, an adhesive potting material and/or other bonding material can be used to secure the SIMM board to the housing and/or pot the SIMM within the housing.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate.

Abstract: A circuit board assembly mechanism for assembling a first circuit board in suspension in the circuit board assembly mechanism includes a base and connecting bracket. The base has a pillar extruding from a bottom plate of the base and a side plate bending from a wing of the bottom plate. The pillar is positioned corresponding to a first hole of first circuit board and houses it atop by inserting a fixer through the first hole into the pillar. The connecting bracket has a first end and a second end in opposition to each other for connecting the first circuit board with the side plate of the base by fixing the first end on the first circuit board and restricting the second end on the side plate, thereby assembling the first plate in suspension within the base by the pillar and the connecting bracket and reserving the space between the first circuit board and the bottom plate for assembling a second circuit board.

Abstract: A system includes a memory module formed of a first portion having a first side that directly connects to a mount in the system, which first side is of a first length; and a second portion having a second side, which second side is of a second length, the second length being greater than the first length.

Abstract: A technique for reducing the number of layers in a multilayer circuit board is disclosed. The multilayer circuit board has a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer circuit board. In one embodiment, the technique is realized by forming a first plurality of electrically conductive vias in the multilayer circuit board extending from the surface of the multilayer circuit board to a first of the plurality of electrically conductive signal layers, wherein the first plurality of electrically conductive vias are arranged so as to form a channel in a second of the plurality of electrically conductive signal layers beneath the first plurality of electrically conductive vias.

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated in to electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material. The dielectric is photoimaged and etched to provide one or more recesses or openings for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric is described as well as the method of manufacturing the same.

Abstract: Disclosed is an electronics packaging system, which provides for a high density assembly of groups of similar solid state part packages. The system provides a novel method for interconnecting the signal paths, structurally assembling and supporting the parts, and removing heat generated within the components. The system approach disclosed typically starts at the level of assembling pre-packaged parts into modules, and permeates through to the printed circuit board and box levels of assembly. The system is applicable, but not limited to, solid state memory device packaging, which typically consists of many similar parts interconnected in a matrix bus type configuration. The assembly of a building block of numerous memory components allows for the modular construction of large amounts of solid state memory.

Abstract: An interposer includes a substrate having opposing surfaces. Conductive terminals are disposed on both surfaces, and conductive terminals on one surface are electrically connected to conductive terminals on the opposing surface. Elongate, springable, conducive interconnect elements are fixed to conductive terminals on both surfaces.