Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.

Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers and a plurality of insulating layers alternately stacked on the substrate. The plurality of contact parts are provided in a protruding shape on respective end parts of the plurality of electrode layers. The plurality of contact parts do not overlap each other in the stacking direction. The plurality of contact parts are displaced in a surface direction of the substrate. The plurality of plugs extends from the respective contact parts toward the respective circuit interconnections and electrically connects the respective contact parts with the respective circuit interconnections.

Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing a semiconductor device according to one embodiment includes a step of cutting, in a dicing region arranged between two chip regions adjacent to each other, a wafer along an extending direction of the dicing region. The dicing region has therein a plurality of metal patterns in a plurality of columns. In the step of cutting the wafer, one or more of the columns of metal patterns formed in a plurality of columns are removed, and the metal patterns of the column(s) different from the above-mentioned one or more of the columns are not removed.

Abstract: Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.

Abstract: There is provided a method for manufacturing a semiconductor device, including forming an insulating film having a prescribed composition and a prescribed film thickness on a substrate by alternately performing the following steps prescribed number of times: supplying one of the sources of a chlorosilane-based source and an aminosilane-based source to a substrate in a processing chamber, and thereafter supplying the other source, to form a first layer containing silicon, nitrogen, and carbon on the substrate; and supplying a reactive gas different from each of the sources, to the substrate in the processing chamber, to modify the first layer and form a second layer.

Abstract: A device comprises: a first plurality of fins on a semiconductor substrate, the first plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a second plurality of fins on the semiconductor substrate, the second plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a chemox layer deposited on lower portions of the fins of the first plurality of fins; and a dielectric layer deposited on the fins of the second plurality of fins. The dielectric layer is thicker than the chemox layer.

Abstract: In the disclosed methods, integrated circuit (IC) dice are manufactured from a common specification, and the IC dice are tested for defective circuitry. Respective defect sets are generated to indicate defective circuitry in the IC die. The dice are assigned to bins based on the respective defect sets. For each bin, all IC dice assigned to the bin have equivalent respective defect sets. Product definitions are provided, and each product definition indicates a respective set of circuitry required for a corresponding product. Respective sets of packages are manufactured for each product. In the manufacturing of each package of a respective set of packages for each product, one or more IC dice are selected from a subset of the plurality of bins such that the IC dice have respective defect sets allowed by the product definition of the product. The selected IC dice are then manufactured into the package.

Abstract: A semiconductor device manufacturing method includes (a) forming a buried diffusion layer of a first conductivity type in a semiconductor substrate of a second conductivity type, (b) forming a first impurity region by implanting an impurity of the first conductivity type, (c) diffusing the buried diffusion layer and the first impurity region to an extent that the buried diffusion layer and the first impurity region are not connected by performing a first thermal process on the semiconductor substrate, (d) forming a second impurity region by implanting an impurity of the first conductivity type at a concentration higher than that of in step (b), and (e) diffusing the buried diffusion layer, the first impurity region, and the second impurity region by performing a second thermal process on the semiconductor substrate.

Abstract: Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion.

Abstract: A system and method for precision cutting using multiple laser beams is described. The system and method includes a combination of optical components that split the output of a single laser into multiple beams, with the power, polarization status and spot size of each split beam being individually controllable, while providing a circularly polarized beam at the surface of a work piece to be cut by the laser beam. A system and method for tracking manufacture of individual stents is also provided.

Abstract: Integrated optical waveguides and methods for the production thereof which have a patterned upper cladding with a defined opening to allow at least one side or at least one end of a light transmissive element to be air clad. The at least one side or at least one end is, for preference, a lens structure unitary with the waveguide or a bend. Also provided is a method of fabricating an optical waveguide with a patterned cladding.

Abstract: A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.

Abstract: The ion implantation method includes setting an ion beam scanning speed and a mechanical scanning speed of an object during ion implantation using hybrid scan in advance and implanting ions based on the set ion beam scanning speed and the set mechanical scanning speed of the object. In the setting in advance, each of the ion beam scanning speeds is set based on each of ion beam scanning amplitudes changing severally according to a surface outline of an object which is irradiated with the ions so that an ion beam scanning frequency is maintained constant for any of ion beam scanning amplitudes, and the mechanical scanning speed of the object corresponding to the ion beam scanning speed is set so that an ion implantation dose per unit area to be implanted into the surface of the object is maintained constant.

Abstract: According to one embodiment, there is provided a method for manufacturing a photovoltaic cell. The method includes forming a structure including a pair of electrodes which are arranged apart from each other, and a hetero-junction type photoelectric conversion layer interposed between the electrodes and containing a p-type semiconductor and a n-type semiconductor, and annealing the photoelectric conversion layer thermally while applying an AC voltage having a frequency of 0.01 kHz or more and less than 1 kHz to control a mixed state of the p-type semiconductor and n-type semiconductor in the photoelectric conversion layer.

Abstract: According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip.

Abstract: In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.

Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.

Abstract: The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract: A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer.