Patents Examined by Michael Trinh
  • Method and device for producing a semiconductor layer
    Patent number: 8956906
    Abstract: The invention relates to a method and a device for producing a semiconductor layer. The problem addressed is that of increasing the deposition rate of the layer constituents and significantly improving the efficiency of a resulting solar cell. At the same time, the material costs are intended to be reduced. The problem is solved by virtue of the fact that, in a vacuum chamber, metal evaporator sources release Cu, In and/or Ga or the chalcogenide compounds, the latter are focused as metal vapor jets onto the substrate, and Se and/or S emerge(s) in an ionized fashion from a chalcogen low-energy wide-beam ion source and this beam is focused onto the surface of the substrate in such a way that it overlaps the metal vapor jets. A device for carrying out the method is described.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 17, 2015
    Assignee: Solarion AG
    Inventors: Hendrik Zachmann, Karsten Otte, Horst Neumann, Frank Scholze, Lutz Pistol
  • Fabrication method for organic EL device
    Patent number: 8956898
    Abstract: The fabrication method for an organic EL device according to the invention includes: forming a third insulating layer on a first insulating layer; removing the third insulating layer in a first pixel region by etching the third insulating layer; forming a second insulating layer that has different thicknesses in a first pixel and a second pixel and has a flat first surface by forming a precursor insulating layer to continuously cover a first reflection film and a second reflection film and then planarizing an upper surface of the precursor insulating layer; and forming a first pixel electrode and a second pixel electrode on the first surface of the second insulating layer. The first insulating layer is slower in the rate at which the layer is removed by etching than the third insulating layer.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: February 17, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Hisakatsu Sato, Satoshi Murata
  • Embedded test structure for trimming process control
    Patent number: 8956886
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
  • Transistor and method for forming the same
    Patent number: 8952429
    Abstract: The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: February 10, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijong Luo, Huilong Zhu
  • III-nitride power device
    Patent number: 8952352
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: February 10, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Method of forming transistors with ultra-short gate feature
    Patent number: 8946003
    Abstract: A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 3, 2015
    Assignee: SK hynix Inc.
    Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
  • Lighting elements
    Patent number: 8941143
    Abstract: An OLED lighting element comprises a substrate bearing an OLED structure extending laterally over said substrate and sandwiched between first and second electrode layers. The first electrode layer defines a plurality of electrically conductive tracks and said second electrode layer comprises a substantially continuous electrically conducting layer. The OLED lighting element has an electrical bus-bar connected to said electrically conductive tracks extending substantially completely along the or each lateral edge of said lighting element. The electrically conductive tracks run in a radial direction from a laterally central location within said lighting element towards said bus-bar along said lateral edges of said lighting element. A said track subdivides into a plurality of tracks with increasing distance from said central location. This arrangement makes more efficient use of the conductive tracks.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: January 27, 2015
    Assignee: Cambridge Display Technology Limited
    Inventor: Euan Smith
  • Sealed semiconductor device having adhesive patch with inwardly sloped side surfaces
    Patent number: 8941226
    Abstract: A semiconductor device has an external terminal formed through the use of an electrolysis plating method. A front surface of a semiconductor wafer is placed over a front surface of a first support heated to a first temperature. An adhesive sheet is then bonded to a back surface of the semiconductor wafer, after which the semiconductor wafer is subjected to heat treatment at a second temperature higher than the first temperature. After the semiconductor wafer and the adhesive sheet are cut along cutting regions, a plurality of semiconductor chips each having an adhesive patch bonded thereto are obtained. A mother substrate is placed over a front surface of a second support heated to a third temperature and the semiconductor chips are fixed to an upper surface of the mother substrate via the adhesive patch.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroaki Narita
  • Method for fabricating a III-nitride semiconductor device
    Patent number: 8940567
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 27, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Apparatus and method for placing solder balls
    Patent number: 8937008
    Abstract: A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 20, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Yonggang Jin
  • Methods for forming a round bottom silicon trench recess for semiconductor applications
    Patent number: 8932947
    Abstract: Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Joo Won Han, Kee Young Cho, Han Soo Cho, Sang Wook Kim, Anisul H. Khan
  • Array substrate for fringe field switching mode liquid crystal display device
    Patent number: 8933460
    Abstract: A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line, a gate electrode and a pixel electrode on a substrate; forming a gate insulating layer; forming a data line, source and drain electrodes, and a semiconductor layer on the gate insulating layer, the drain electrode overlapping the pixel electrode; forming a passivation layer on the data line, the source and drain electrodes; forming a contact hole exposing the drain electrode and the pixel electrode by patterning the passivation layer and the gate insulating layer; and forming a common electrode and a connection pattern on the passivation layer, wherein the common electrode includes bar-shaped openings and a hole corresponding to the contact hole, and the connection pattern is disposed in the hole, is spaced apart from the common electrode and contacts the drain electrode and the pixel.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: January 13, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Jeong-Oh Kim, Jung-Sun Beak
  • Wafer with spacer including horizontal member
    Patent number: 8933535
    Abstract: A method of forming an insulating spacer is disclosed that includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion. A wafer is also disclosed.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Andrew B. Graham, Gary Yama, Gary O'Brien
  • Wafer processing method
    Patent number: 8927395
    Abstract: In a wafer processing method, a modified layer is formed inside a wafer along planned dividing lines by irradiating the wafer with a laser beam with such a wavelength as to be transmitted through the wafer from the back surface side of the wafer along the dividing lines. A first modified layer is formed near the back surface of the wafer by irradiating the wafer with the light focal point of the laser beam positioned near the back surface of the wafer. The wafer is then irradiated with the light focal point of the laser beam positioned on the front surface side. Then plural second modified layers are formed in a multi-layering manner with sequential movement of the light focal point toward an area leading to the first modified layer. The wafer is divided into individual devices along the dividing lines by applying an external force to the wafer.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 6, 2015
    Assignee: Disco Corporation
    Inventor: Masaru Nakamura
  • Methods for producing and placing wavelength converting structures
    Patent number: 8921130
    Abstract: Methods for producing and placing wavelength converting structures for use in a solid state lighting assembly are disclosed. The wavelength converting structures may take the form of thin film converters including a substrate and one or more thin films of wavelength conversion material.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: December 30, 2014
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Darshan Kundaliya, Jeffery Serre
  • Deposition of amorphous silicon-containing films
    Patent number: 8921205
    Abstract: Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. Preferably, the deposited amorphous silicon-containing film is annealed to produce crystalline regions over all or part of an underlying substrate.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: December 30, 2014
    Assignee: ASM America, Inc.
    Inventor: Michael A. Todd
  • Wafer edge warp supression for thin wafer supported by tape frame
    Patent number: 8912075
    Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: December 16, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Device having a multilayered structure and method of fabricating thereof
    Patent number: 8906707
    Abstract: The invention provides a multilayered device and the method for fabricating the same. The multilayered device comprises a substrate, a first layer deposited on the substrate, a second layer deposited on the first layer, and a third layer deposited on the second layer. The coverage of the second layer is determined by a rate of crystallization of the third layer. The rate of crystallization of the third layer is determined by measuring X-ray diffraction of the device.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: December 9, 2014
    Assignee: Industry-University Cooperation Foundation Sogang University
    Inventors: Young Joo Lee, Hyunjung Kim
  • Multiple beam laser system for forming stents
    Patent number: 8901452
    Abstract: A system and method for precision cutting using multiple laser beams is described, The system and method includes a combination of optical components that split the output of a single laser into multiple beams, with the power, polarization status and spot size of each split beam being individually controllable, while providing a circularly polarized beam at the surface of a work piece to be cut by the laser beam. A system and method for tracking manufacture of individual stents is also provided.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 2, 2014
    Assignee: Abbott Cardiovascular Systems, Inc.
    Inventors: Li Chen, Randolf Von Oepen
  • Organic light-emitting display having light blocking layer formed over pixel defining layer
    Patent number: 8900898
    Abstract: An organic light-emitting display includes a substrate including a pixel region and a transistor region; a first transparent electrode and a second transparent electrode formed over the pixel region and the transistor region of the substrate, respectively; a gate electrode formed over the second transparent electrode; a gate insulating film formed over the gate electrode; a semiconductor layer formed over the gate insulating film; a source and drain electrode having an end connected to the semiconductor layer and the other end connected to the first transparent electrode; a pixel defining layer disposed over the source and drain electrode to cover the source and drain electrode and having an opening disposed over the first transparent electrode; a light-blocking layer formed over the pixel defining layer; and an organic light-emitting layer formed over the first transparent electrode.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong-Woo Park