Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract: A layer of microscopic, 3-terminal transistors is printed over a first conductor layer so that bottom electrodes of the transistors electrically contact the first conductor layer. A first dielectric layer overlies the first conductor layer, and a second conductor layer over the first dielectric layer contacts intermediate electrodes on the transistors between the bottom electrodes and top electrodes. A second dielectric layer overlies the second conductor layer, and a third conductor layer over the second dielectric layer contacts the top electrodes. The devices are thus electrically connected in parallel by a combination of the first conductor layer, the second conductor layer, and the third conductor layer. Separate groups of the devices may be interconnected to form more complex circuits. The resulting circuit may be a very thin flex-circuit.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.

Abstract: An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die (157) and surrounding scribe grid (156) to a test head (155) which is positioned over a wafer (160) in alignment with a die under test (163) and surrounding scribe grid (161, 165), such that one or more optical deflection mirrors (152, 154) in the test head scribe grid (156) are aligned with one or more optical deflection mirrors (162, 164) in the scribe grid (161, 165) for the die under test (163) to enable optical die probe testing on the die under test (163) by directing a first optical test signal (158) from the production test die (157), through the first and second optical deflection mirrors (e.g., 152, 162) and to the first die.

Abstract: A method of manufacturing a light emitting device having a plurality of nano-light emitting structures is provided. The method comprises depositing a first conductivity-type semiconductor material on a substrate to form a base layer. A mask having a plurality of openings is formed on the base layer. The first conductivity-type nitride semiconductor material is deposited in the openings of the mask to form a plurality of nanocores having a main portion bounded by the mask and an exposed tip portion. A current blocking layer is deposited on the tip portion of the nanocores. A portion of the mask is removed to expose the main portion of the nanocore. An active material layer is deposited on the plurality of nanocores. A second conductivity-type nitride semiconductor layer is deposited on the active material layer.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Abstract: Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.

Abstract: A method for forming an oxide layer on a substrate is described, wherein a plasma is generated adjacent to at least one surface of the substrate by means of microwaves from a gas containing oxygen, wherein the microwaves are coupled into the gas by a magnetron via at least one microwave rod, which is arranged opposite to the substrate and comprises an outer conductor and an inner conductor. During the formation of the oxide layer, the mean microwave power density is set to P=0.8-10 W/cm2, the plasma duration is set to t=0.1 to 600 s, the pressure is set to p=2.67-266.64 Pa (20 to 2000 mTorr) and a distance between substrate surface and microwave rod is set to d=5-120 mm. The above and potentially further process conditions are matched to each other such that the substrate is held at a temperature below 200° C. and an oxide growth is induced on the surface of the substrate facing the plasma.

Abstract: A vertical-channel semiconductor device includes an active pillar including a channel region, a gate located at a sidewall of the active pillar, a buried bit-line formed below the active pillar, and an insulation film formed below the buried bit-line. Some parts of the buried bit-line are replaced with an insulation film, such that a bit-line junction leakage is prevented.

Abstract: One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes exposing a portion of a surface of a semiconductor substrate between a first spacer and a second spacer. The method further includes selectively forming a dielectric layer on the portion of the surface. A metal gate is formed over the dielectric layer and between the first spacer and the second spacer. The metal gate contacts the first spacer and the second spacer.

Abstract: A method for reducing an internal pressure of a vacuum chamber while preventing impurity contamination within the vacuum chamber as much as possible is provided. The method includes: rough pumping reducing an internal pressure of a vacuum chamber by using a roughing pump, the roughing pump being a mechanical pump that is capable of reducing the internal pressure of the vacuum chamber to be less than 15 Pa; main pumping reducing the internal pressure of the vacuum chamber by using a main pump after the rough pumping, the main pump being a non-mechanical pump. Transition from the rough pumping to the main pumping is performed when the internal pressure of the vacuum chamber is no less than 15 Pa.

Abstract: There is provided a substrate processing apparatus, including a processing chamber configured to house a substrate, a first source supply system configured to supply a chlorosilane-based source to the substrate in the processing chamber, a second source supply system configured to supply an aminosilane-based source to the substrate in the processing chamber and a reactive gas supply system configured to supply a reactive gas different from each of the sources, to the substrate in the processing chamber. The substrate processing apparatus further includes a controller configured to control the first source supply system, the second source supply system, and the reactive gas supply system, so that a process of forming an insulating film on the substrate is performed by an alternating process.

Abstract: A method of manufacturing a light-emitting diode package is illustrated. A light-emitting diode chip is manufactured. A material layer is formed on side surfaces and a rear surface of the light-emitting diode chip. The material layer is then oxidized to convert the material layer into an oxidized layer to form a reflective layer on the side surfaces and the rear surface of the light-emitting diode chip. The light-emitting diode chip is packaged.

Abstract: A method of forming a patterned substrate includes casting a layer of a block copolymer having an intrinsic glass transition temperature Tg, on a substrate to form a layered substrate. The method also includes heating the layered substrate at an annealing temperature, which is greater than about 50° C. above the intrinsic glass transition temperature Tg of the block copolymer, in a first atmosphere. The method further includes thermally quenching the layered substrate to a quenching temperature lower than the intrinsic glass transition temperature Tg, at a rate of greater than about 50° C./minute in a second atmosphere. The method further includes controlling an oxygen content in the first and second atmospheres to a level equal to or less than about 50 ppm to maintain the annealing and quenching temperatures below a thermal degradation temperature Td of the block copolymer.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A system and method for precision cutting using multiple laser beams is described. The system and method includes a combination of optical components that split the output of a single laser into multiple beams, with the power, polarization status and spot size of each split beam being individually controllable, while providing a circularly polarized beam at the surface of a work piece to be cut by the laser beam. A system and method for tracking manufacture of individual stents is also provided.

Abstract: A method of manufacturing a semiconductor device uses a mounting jig having an insulated circuit board positioning jig, a tubular contact element positioning jig having a plurality of positioning holes formed at predetermined positions to insert a tubular contact element, and a tubular contact element press-down jig. By the insulated circuit board positioning jig and tubular contact element positioning jig, an insulated circuit board and the tubular contact elements are positioned, and the tubular contact elements are soldered to the insulated circuit board while being pressed down by the tubular contact element press-down jig.

Abstract: A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer.