Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.

Abstract: A light emitting device according to embodiments includes a light emitting element emitting light having a peak wavelength of 425 nm or more and 465 nm or less, a first phosphor emitting light having a peak wavelength of 485 nm or more and 530 nm or less, a second phosphor emitting light having a peak wavelength longer than that of the first phosphor, and a third phosphor emitting light having a peak wavelength longer than that of the second phosphor. Then, when the peak wavelength of the light emitting element is ?0 (nm) and the peak wavelength of the first phosphor is ?1 (nm), a relation of 30??1??0?70 is satisfied.

Abstract: In various embodiments, photovoltaic devices incorporate discontinuous passivation layers (i) disposed between a thin-film absorber layer and a partner layer, (ii) disposed between the partner layer and a front contact layer, and/or (iii) disposed between a back contact layer and the thin-film absorber layer.

Abstract: According to one embodiment, there is provided a method for manufacturing a photovoltaic cell. The method includes forming a structure including a pair of electrodes which are arranged apart from each other, and a hetero-junction type photoelectric conversion layer interposed between the electrodes and containing a p-type semiconductor and a n-type semiconductor, and annealing the photoelectric conversion layer thermally while applying an AC voltage having a frequency of 0.01 kHz or more and less than 1 kHz to control a mixed state of the p-type semiconductor and n-type semiconductor in the photoelectric conversion layer.

Abstract: A phosphor mixture includes a first phosphor and a second phosphor, wherein an emission spectrum of the first phosphor has a relative intensity maximum in a yellow spectral range and an emission spectrum of the second phosphor has a relative intensity maximum in a red spectral range, the first phosphor corresponds to the following chemical formula: (LuxY1?x)3(Al1?yGay)5O12:Ce3+, where x is greater than or equal to 0 and less than or equal to 1 and where y is greater than or equal to 0 and less than or equal to 0.4, and the phosphor mixture is formed from a plurality of particles, which includes a plurality of particles of the first phosphor and a plurality of particles of the second phosphor.

Abstract: The fabrication method for an organic EL device according to the invention includes: forming a third insulating layer on a first insulating layer; removing the third insulating layer in a first pixel region by etching the third insulating layer; forming a second insulating layer that has different thicknesses in a first pixel and a second pixel and has a flat first surface by forming a precursor insulating layer to continuously cover a first reflection film and a second reflection film and then planarizing an upper surface of the precursor insulating layer; and forming a first pixel electrode and a second pixel electrode on the first surface of the second insulating layer. The first insulating layer is slower in the rate at which the layer is removed by etching than the third insulating layer.

Abstract: A method of forming a patterned substrate includes casting a layer of a block copolymer having an intrinsic glass transition temperature Tg, on a substrate to form a layered substrate. The method also includes heating the layered substrate at an annealing temperature, which is greater than about 50° C. above the intrinsic glass transition temperature Tg of the block copolymer, in a first atmosphere. The method further includes thermally quenching the layered substrate to a quenching temperature lower than the intrinsic glass transition temperature Tg, at a rate of greater than about 50° C./minute in a second atmosphere. The method further includes controlling an oxygen content in the first and second atmospheres to a level equal to or less than about 8 ppm to maintain the annealing and quenching temperatures below a thermal degradation temperature Td of the block copolymer.

Abstract: A method includes forming a mask layer forming a first photo resist over the mask layer, performing a first patterning step on the first photo resist, and performing a first etching step on the mask layer using the first photo resist as an etching mask. The first photo resist is then removed. The method further includes forming a particle-fixing layer on a top surface and sidewalls of the mask layer, forming a second photo resist over the particle-fixing layer and the mask layer, performing a second patterning step on the second photo resist, and performing a second etching step on the particle-fixing layer and the mask layer using the second photo resist as an etching mask. The particle-fixing layer is etched through. A target layer underlying the mask layer is etched using the mask layer as an etching mask.

Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract: A layer of microscopic, 3-terminal transistors is printed over a first conductor layer so that bottom electrodes of the transistors electrically contact the first conductor layer. A first dielectric layer overlies the first conductor layer, and a second conductor layer over the first dielectric layer contacts intermediate electrodes on the transistors between the bottom electrodes and top electrodes. A second dielectric layer overlies the second conductor layer, and a third conductor layer over the second dielectric layer contacts the top electrodes. The devices are thus electrically connected in parallel by a combination of the first conductor layer, the second conductor layer, and the third conductor layer. Separate groups of the devices may be interconnected to form more complex circuits. The resulting circuit may be a very thin flex-circuit.

Abstract: A method of manufacturing a light emitting device having a plurality of nano-light emitting structures is provided. The method comprises depositing a first conductivity-type semiconductor material on a substrate to form a base layer. A mask having a plurality of openings is formed on the base layer. The first conductivity-type nitride semiconductor material is deposited in the openings of the mask to form a plurality of nanocores having a main portion bounded by the mask and an exposed tip portion. A current blocking layer is deposited on the tip portion of the nanocores. A portion of the mask is removed to expose the main portion of the nanocore. An active material layer is deposited on the plurality of nanocores. A second conductivity-type nitride semiconductor layer is deposited on the active material layer.

Abstract: The invention relates to a method for producing a photovoltaic solar cell having a front side designed for coupling in light, comprising the following method steps: A Producing a plurality of cutouts in a semiconductor substrate of a base doping type, B Producing one or more emitter regions of an emitter doping type at least at the front side of the semiconductor substrate, wherein the emitter doping type is opposite to the base doping type, C Applying an electrically insulating insulation layer and D Producing metallic feed through structures in the cutouts, at least one metallic base contact structure at the rear side of the solar cell, which is formed in an electrically conductive manner with the semiconductor substrate in a base doping region, at least one metallic front-side contact structure at the front side of the solar cell, which is formed in an electrically conductive manner with the emitter region at the front side of the semiconductor substrate, and at least one rear-side contact structure at the

Abstract: Provided is a method of manufacturing a flexible display, which can simplify manufacturing processes and reduce manufacturing expenses. A method of manufacturing a flexible display according to one exemplary embodiment of the present invention may include: forming a sacrificial layer on a carrier substrate; forming a flexible substrate on the sacrificial layer; forming a TFT array on the flexible substrate; etching the sacrificial layer to separate the flexible substrate from the carrier substrate; attaching the flexible substrate to an adhesive roll; and attaching the flexible substrate, which has been attached to the adhesive roll, to a rear substrate.

Abstract: A compliant bonding structure is disposed between a semiconductor device and a mount. In some embodiments, the device is a light emitting device. When the semiconductor light emitting device is attached to the mount, for example by providing ultrasonic energy to the semiconductor light emitting device, the compliant bonding structure collapses to partially fill a space between the semiconductor light emitting device and the mount. In some embodiments, the compliant bonding structure is plurality of metal bumps that undergo plastic deformation during bonding. In some embodiments, the compliant bonding structure is a porous metal layer.

Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.

Abstract: A donor substrate may include a base layer, a light to heat conversion layer disposed on the base layer, a buffer layer disposed on the light to heat conversion layer, an organic transfer layer disposed on the buffer layer, and a tightening member disposed on a peripheral portion of the organic transfer layer. The tightening member may include an adhesive film having an adhesion strength controlled by an irradiation of an ultraviolet ray. Process failures for manufacturing an organic light emitting display device may be prevented by the donor substrate, so that the organic light emitting display device may ensure improved performances.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.

Abstract: A method of manufacturing an organic light-emitting display device is provided. An alignment master member is loaded on a moving unit. An organic layer deposition assembly is pre-aligned to the alignment master member. After the pre-aligning of the organic layer deposition assembly, a substrate is loaded on the moving unit. The organic layer deposition assembly is aligned to the substrate positioned as is after the loading of the substrate. An organic layer is formed on the substrate while the moving unit is moving along the moving direction. While the moving unit is moving along the moving direction, the organic layer deposition assembly is adjusted so that an interval between the organic layer deposition assembly and part of the substrate is maintained as substantially constant. The part of the substrate receives a deposition material emitted from the organic layer deposition assembly to form the organic layer.