Abstract: A semiconductor device includes a semiconductor body having a first surface defining a vertical direction and a source metallization arranged on the first surface. In a vertical cross-section the semiconductor body further includes: a drift region of a first conductivity type; at least two compensation regions of a second conductivity type each of which forms a pn-junction with the drift region and is in low resistive electric connection with the source metallization; a drain region of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the drift region, and a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and includes at least one of a floating field plate and a floating semiconductor region of the second conductivity type forming a pn-junction with the third semiconductor layer.

Abstract: A method for depositing a layer of phosphor-containing material on a plurality of LED (light-emitting diode) dies on a wafer includes disposing a layer of dry photoresist film over a plurality of LED dies on a wafer, disposing a mask layer over the dry photoresist film, and patterning the dry photoresist film to form a plurality of openings in the dry photoresist film to expose a top surface of each of the LED dies. The method also includes depositing a phosphor-containing material on the exposed top surface of each the LED dies using a screen printing process, and removing the patterned dry photoresist film.

Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.

Abstract: A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner.

Abstract: A thermoelectric element module has P-type thermoelectric materials and N-type thermoelectric materials alternately joined between a pair of substrates. The thermoelectric materials include a thermoelectric mixture powder in which a thermoelectric material powder and a low-melting metal powder are mixed at a predetermined ratio. The thermoelectric mixture powder is thermally treated at a temperature lower than a melt point of the thermoelectric material, the thermoelectric mixture powder is formed as the low-melting metal is melted, and at the same time both ends of the thermoelectric materials are joined to the pair of substrates. A method for manufacturing such a thermoelectric material is also provided.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

Abstract: Mechanisms are provided for chip (e.g., semiconductor chip) identification (e.g., low cost secure identification). In one example, a method of manufacturing for implementing integrated chip identification is provided. In another example, a method of using a chip with an integrated identification is provided.

Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes layering metal and insulator materials on a sacrificial material formed on a substrate. The method further includes masking the layered metal and insulator materials. The method further includes forming an opening in the masking which overlaps with the sacrificial material. The method further includes etching the layered metal and insulator materials in a single etching process to form the beam structure, such that edges of the layered metal and insulator material are aligned. The method further includes forming a cavity about the beam structure through a venting.

Abstract: Embodiments of the present invention provide methods and apparatus for forming a patterned magnetic layer for use in magnetic media. According to embodiments of the present application, a silicon oxide layer formed by low temperature chemical vapor deposition is used to form a pattern in a hard mask layer, and the patterned hard mask is used to form a patterned magnetic layer by plasma ion implantation.

Abstract: Provided is a method of manufacturing a solar cell. The method includes: preparing a substrate with a rear electrode; and forming a copper indium gallium selenide (CIGS) based light absorbing layer on the rear electrode at a substrate temperature of room temperature to about 350° C., wherein the forming of the CIGS based light absorbing layer includes projecting an electron beam on the CIGS based light absorbing layer.

Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Abstract: A thin film photovoltaic device includes a substrate and a first conductive layer coupled to the substrate. The first conductive layer includes at least one first groove extending through a first portion of the first conductive layer to a portion of the substrate. The device also includes at least one semiconductor layer coupled to a remaining portion of the first conductive layer and the portion of the substrate. The at least one semiconductor layer includes a plurality of non-overlapping vias, each via extending through a portion of the at least one semiconductor layer to a portion of the first conductive layer. The device further includes a second conductive layer coupled to a remaining portion of the at least one semiconductor layer and portions of the first conductive layer. The second conductive layer includes at least one second groove extending through a portion of the second conductive layer to a portion of the at least one semiconductor layer.

Abstract: Provided are methods of forming a ternary metal nitride film and more specifically, a TaSiN film. A metal nitride film, or TaN film, is deposited on a substrate with plasma treatment. A SiN layer is deposited on the metal nitride, or TaN, film to form a metal-SiN, or TaSiN, film. The film is then annealed to provide a metal nitride film with stable resistivity.

Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.

Abstract: A backside illumination (BSI) CMOS image sensing process includes the following steps. A substrate having an active side is provided. A curving process is performed to curve the active side. A reflective layer is formed on the active side, so that at least a curved mirror is formed on the active side.

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

Abstract: A method for profiling a film stack includes receiving a film stack having an insulation layer, a dielectric hard mask layer, and a patterned metal hard mask layer. The pattern in the patterned metal hard mask layer is transferred to the dielectric hard mask layer using a first dry etching process. The pattern in the dielectric hard mask layer is then transferred to the insulation layer using a second dry etching process including one or more halogen-containing gases. The second etching process etches the insulation layer and removes a portion of the patterned metal hard mask layer, which exposes a corner of the underlying dielectric hard mask layer. Portions of the dielectric hard mask layer that overhang the insulation layer are removed using a third dry etching process including a process composition that is more selective to the dielectric hard mask layer relative to the insulation layer.

Abstract: Methods and apparatus for manufacturing a semiconductor light-emitting device that emits white light by forming a phosphor layer on an emission surface of the semiconductor light-emitting device at a wafer-level. The method includes: forming a plurality of light-emitting devices on a wafer; thinning the wafer, on which the plurality of light-emitting devices are formed; disposing the thinned wafer on a carrier film; and forming a phosphor layer on an emission surface of the plurality of light-emitting devices on the wafer.