Abstract: The semiconductor device comprising a P type semiconductor substrate, first and second P-wells, an N-well between the first and the second P-wells, trench element-isolating films for electrically separating the wells from each other and the first P-well from the P type semiconductor substrate, and an N type buried region formed below a first P-well between the trench element-isolating films, which is suitable to high integration and improved in operating speed.

Abstract: A direct laser ablation process is disclosed for forming thin film transistors on liquid crystal matrix for enabling typically color presentation from a flat panel display. The thin film transistor is of the type having an active matrix addressing scheme wherein a capacitor when charged turns on and maintains in the "on" state a field effect transistor to permit passage of light through a liquid crystal display. All patterning of the display is done either by utilizing deposition, direct ablation of an etch block followed by etching, or more preferably deposition followed by direct laser ablation. In the preferred embodiment, aluminum channels are made by deposition followed by a direct laser ablation. Anodizing follows with deposition of a silicon-nitrogen layer. With respect to the capacitor, indium tin oxide is deposited to complete a matrix capable of selectively strobing and charging the capacitor for each matrix element.

Abstract: On a semi-insulative GaAs substrate, a channel layer, an electron supply layer, a threshold voltage controlling layer, an etching stop layer, a contact layer and an insulation layer are grown. By etching the insulation layer, gate openings are formed in an E-type element region and a D-type element region. With taking the gate opening as mask, dry etching is performed for the contact layer to form openings. On the inner periphery of the openings, side wall insulation layers are formed. With masking the gate opening in the D-type element region, and with taking the side wall insulation layer as mask, the etching stop layer is etched by wet etching, and threshold voltage controlling layer is etched by isotropic dry etching. After formation of the gate electrodes, source and drain electrodes are formed. By this, damaging of crystal upon formation of recess portion by etching is eliminated to prevent degradation of characteristics. Also, a source resistance can be lowered.

Abstract: A method of fabricating a semiconductor device forms a resist pattern for a gate electrode or the like on a semiconductor device in such a manner that only a fine resist pattern is formed on a resist member by an electron beam lithography and other resist patterns are formed on the same resist member by an optical lithography.

Abstract: In etching a polysilicon layer above a gate electrode layer, a portion of the gate electrode layer is left thereunder. The etching process of that polysilicon layer and that gate electrode layer is carried out in two steps of etching the polysilicon layer and an interlayer insulating layer, and etching the gate electrode layer and the gate oxide film. Therefore, the amount that is removed from an SOI layer can be suppressed in the manufacturing process thereof.

Abstract: A method of fabricating an asymmetric lightly doped drain transistor device. The device's drain region is shielded with a barrier layer when ion implantation is applied to a implant a highly doped source region. A large angle implantation then follows to form a lightly doped pocket region adjacent to the highly doped source region. The implantation forming the pocket region increases the doping concentration along the device's source side which increases the device's threshold voltage diminishing short channel effects.

Abstract: A superconducting device comprising a substrate having a principal surface, a superconducting source region and a superconducting drain region formed of an oxide superconductor on the principal surface of the substrate separated from each other, an extremely thin superconducting channel formed of the oxide superconductor between the superconducting source region and the superconducting drain region. The superconducting channel electrically connects the superconducting source region to a superconducting drain region, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device comprises a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel, and non-superconducting oxide layers having a similar crystal structure to that of the oxide superconductor.

Abstract: An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

Abstract: Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long charge carrier life expectancy. An advantage is achieved that the controllable power semiconductor component has a temperature-independent tail current, despite a low on-state dc resistance and a high blocking voltage.

Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.

Abstract: A method for fabricating a MOS transistor includes forming an oxide layer over a silicon substrate of a first conductivity type. A gate electrode is formed over the oxide layer. Ions of a second conductivity type are implanted into the silicon substrate to form lightly-doped source/drain regions. Impurity-containing spacers are formed on sidewalls of the oxide layer and the gate electrode. The spacers are thermally processed to drive impurities of a first conductivity type into the source/drain regions. Finally, ions of a second conductivity type are implanted into the substrate to form heavily-doped source/drain regions.

Abstract: A method of forming an elevated source/drain structure with a solid phase diffused source/drain extension is described. A semiconductor substrate is provided having n-channel and p-channel active areas separated by isolation areas. Gate electrodes are formed overlying a gate oxide layer over each of the active areas. First spacers are formed on the sidewalls of the gate electrodes wherein the first spacers have a first dopant concentration. The first spacers in the p-channel active area are removed and second spacers are formed on the sidewalls of the gate electrodes in the p-channel active area wherein the second spacers have a second dopant concentration different from the first dopant concentration. An epitaxial layer is grown on the surface of the semiconductor substrate wherein the epitaxial layer forms the elevated source/drain structure. First ions are implanted into the n-channel active area and second ions are implanted into the p-channel active area.

Abstract: An image sensor element having at least one charge storage well 70 and 80, charge transfer structures for transferring charge from one charge storage well 70 to another charge storage well 80, and a charge sensor for sensing charge levels in a charge storage well 70 without removing the charge from the well. Other devices, systems and methods are also disclosed.

Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.

Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal .portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.

Abstract: A method of forming a MOS device having a localized anti-punchthrough region, which is adjacent to but is not in contact with source/drain regions of the MOS device. A trench is formed by depositing a conducting layer on an oxide layer located on a channel region of the MOS device. The trench is used as a self-alignment mask for a subsequent implantation process to form the localized anti-punchthrough region.

Abstract: A process for manufacturing an offset gate structure thin film transistor which includes the steps of forming a first semiconductor layer, e.g., an active layer made of amorphous silicon or polysilicon, on a major surface of a substrate, e.g.

Abstract: A process for fabricating metal-gate CMOS transistors on a semiconductor substrate having a well region therein is disclosed herein. The process comprises the steps of: First forming a shielding layer with designated patterns on the substrate and the well region, and, then, forming first field oxides on the substrate or the well region between the designated patterns of the shielding layer through a thermal oxidation procedure. After that, the first field oxides are removed to expose recesses, and drift regions are formed in the substrate and the well region beneath the recesses. Next, second field oxides are formed above the recesses and the shielding layer are subsequently removed. Then, heavily-doped regions are formed in the substrate and the well region between the drift regions, and lightly-doped regions are formed beneath the heavily-doped region, both of which serve as source/drain regions.

Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250.degree. C. to 400.degree. C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved.

Abstract: A process for formation of a thin film transistor liquid crystal display is disclosed, in which an etch-back type 3-mask process or an etch stopper type 4-mask process is applied, so that the semiconductor layer of the thin film transistor can be isolated from the data line. Consequently, the optical leakage current which aggravates the performance of the transistor is inhibited. Further, the data line is composed of a material which has a low chemical reactivity with ITO, so that a corrosion due to a chemical reaction between the data line and ITO can be eliminated.